DSPIC33FJ128MC710-E/PF Microchip Technology, DSPIC33FJ128MC710-E/PF Datasheet - Page 22
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DSPIC33FJ128MC710-E/PF
Manufacturer Part Number
DSPIC33FJ128MC710-E/PF
Description
IC DSPIC MCU/DSP 128K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
3.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
Specifications of DSPIC33FJ128MC710-E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TQFP, 100-VQFP
For Use With
MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
dsPIC33F
FIGURE 6-1:
6.2
When a supply voltage is applied to the device, a
Power-on Reset is generated. A new Power-on Reset
event is generated if the supply voltage falls below the
device threshold voltage (V
pulse is generated when the rising supply voltage
crosses the POR circuit threshold voltage.
6.3
An Oscillator Start-up Timer (OST) is included to
ensure that a crystal oscillator (or ceramic resonator)
has started and stabilized. The OST is a simple, 10-bit
counter that counts 1024 T
the oscillator clock to the rest of the system. The time-
out period is designated as T
involved every time the oscillator has to restart (i.e., on
Power-on Reset (POR) and wake-up from Sleep). The
Oscillator Start-up Timer is applied to the LP oscillator,
XT and HS modes (upon wake-up from Sleep, POR
and BOR) for the primary oscillator.
DS70155C-page 20
SOSCO
SOSCI
OSC1
OSC2
Power-on Reset
Oscillator Start-up Timer/Stabilizer
(OST)
Internal Fast
RC (FRC)
OSCILLATOR SYSTEM BLOCK DIAGRAM
Secondary
Oscillator
Oscillator
Oscillator
Primary
32 kHz
OSC
POR
OST
cycles before releasing
). An internal POR
. The T
OST
Internal Low-Power
RC (LPRC)
Oscillator
time is
Module
Preliminary
PLL
Secondary Osc
Primary Osc
6.4
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software
malfunction. The WDT is a free-running timer that runs
off the on-chip LPRC oscillator, requiring no external
component. The WDT continues to operate even if the
main processor clock (e.g., the crystal oscillator) fails.
The Watchdog Timer can be “Enabled” or “Disabled”
either through a configuration bit (FWDTEN) in the
Configuration register, or through an SFR bit
(SWDTEN).
Any device programmer capable of programming
dsPIC
PM3 Programmer) allows programming of this and
other configuration bits to the desired state. If enabled,
the WDT increments until it overflows or “times out”. A
WDT time-out forces a device Reset (except during
Sleep).
®
DSC devices (such as Microchip’s MPLAB
Switching
Watchdog Timer (WDT)
Control
Clock
Block
and
F
OSC
© 2005 Microchip Technology Inc.
To Timer1
Divide by 4
F
CY
®