AT32UC3A3128-CTUT Atmel, AT32UC3A3128-CTUT Datasheet - Page 62

• Manufacturer Part Number: AT32UC3A3128-CTUT
• Description: IC MCU 128KB FLASH 144TBGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A3128-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-TBGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, I2S, JTAG, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.10 EBI Timings
These timings are given for worst case process, T = 85⋅C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance.
10.10.1
Table 10-30. SMC Clock Signal
Note:
Table 10-31. SMC Read Signals with Hold Settings
Note:
32072C–AVR32–2010/03
Symbol
1/(t
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
CPSMC
1
2
3
4
5
7
8
9
10
11
12
13
14
16
17
18
1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB.
1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”.
)
SMC Signals
Parameter
SMC Controller Clock Frequency
Parameter
Data Setup before NRD High
Data Hold after NRD High
NRD High to NBS0/A0 Change
NRD High to NBS1 Change
NRD High to NBS2/A1 Change
NRD High to A2 - A23 Change
NRD High to NCS Inactive
NRD Pulse Width
Data Setup before NCS High
Data Hold after NCS High
NCS High to NBS0/A0 Change
NCS High to NBS0/A0 Change
NCS High to NBS2/A1 Change
NCS High to A2 - A23 Change
NCS High to NRD Inactive
NCS Pulse Width
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
NRD Controlled (READ_MODE = 1)
NRD Controlled (READ_MODE = 0)
(nrd hold length - ncs rd hold length) * t
ncs rd hold length - nrd hold length)* t
ncs rd hold length * t
ncs rd hold length * t
ncs rd hold length * t
ncs rd pulse length * t
nrd hold length * t
nrd hold length * t
nrd hold length * t
ncs rd hold length * t
nrd pulse length * t
nrd hold length * t
Min.
11.5
12
0
0
CPSMC
1/(t
CPSMC
CPSMC
CPSMC
CPSMC
AT32UC3A3/A4
Max.
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
cpcpu
(1)
- 1.3
- 1.4
-
-
-
- 2.3
)
- 3.6
1.3
1.3
1.3
-
-
CPSMC
-
CPSMC
2.3
2.3
4
- 1.3
- 2.3
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
62