PIC14000T-04/SS Microchip Technology, PIC14000T-04/SS Datasheet - Page 49

• Manufacturer Part Number: PIC14000T-04/SS
• Description: IC MCU OTP 4KX14 A/D 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 14r

Specifications of PIC14000T-04/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 20
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: Slope A/D
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Processor Series: PIC14000
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 14 bit
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.5.1
In slave mode, the SCLx and SDAx pins must be
configured as inputs (TRISC<7:6> or TRISD<1:0> are
set). The I
the output data when required (slave-transmitter).
When an address is matched or the data transfer from
an address match is received, the hardware
automatically will generate the acknowledge (ACK)
pulse, and then load the I
value in the I
There are two conditions that will cause the I
not to give this ACK pulse. These are if either (or both)
occur:
• the Buffer Full (BF), I
• the Overflow (I
TABLE 7-2:
Status Bits as Data Transfer
1996 Microchip Technology Inc.
before the transfer was received, or
before the transfer was received.
BF
0
1
1
0
SLAVE MODE
is Received
2
C module will override the input state with
2
CSR.
2
COV), I
DATA TRANSFER RECEIVED BYTE ACTIONS
I
2
COV
2
0
0
1
1
CSTAT<0>, bit was set
2
CCON<6> bit was set
2
CBUF with the received
I
2
CSR-> I
Yes
2
No
No
No
C module
2
CBUF
Preliminary
Generate ACK Pulse
In this case, the I
I
happens when a data transfer byte is received, given
the status of the BF and I
show the conditions where user software did not
properly clear the overflow condition. The BF flag is
cleared by reading the I
I
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
module is shown in the AC timing specifications.
2
2
2
CBUF, but the I
COV bit is cleared through software.
C specification as well as the requirement of the I
Yes
No
No
No
2
CIF bit is set. Table 7-2 shows what
2
CSR value is not loaded into the
2
COV bits. The shaded boxes
(I
2
CBUF register while the
2
C interrupt if enabled)
PIC14000
Set I
DS40122B-page 49
2
Yes
Yes
Yes
Yes
CIF bit
2
C