PIC16F877T-20I/PT Microchip Technology, PIC16F877T-20I/PT Datasheet - Page 294
![IC MCU FLASH 8KX14 EE 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC16F877T-20I/PT
Manufacturer Part Number
PIC16F877T-20I/PT
Description
IC MCU FLASH 8KX14 EE 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873-04SO.pdf
(218 pages)
5.PIC16F873-04SO.pdf
(5 pages)
6.PIC16F873-04SO.pdf
(5 pages)
Specifications of PIC16F877T-20I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F877T-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- PIC16F873-04SO PDF datasheet #6
- Current page: 294 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4
DS31017A-page 17-18
SSP I
2
C™ Operation
The MSSP module in I
eral call support) and provides interrupts on start and stop bits in hardware to determine a free
bus (multi-master function). The SSP module implements the standard mode specifications as
well as 7-bit and 10-bit addressing.
A “glitch” filter is on the SCL and SDA pins when the pin is an input. This filter operates in both
the 100 KHz and 400 KHz modes. In the 100 KHz mode, when these pins are an output, there
is a slew rate control of the pin that is independent of device frequency.
Figure 17-10: I
Figure 17-11: I
2
2
C Slave Mode Block Diagram
C Master Mode Block Diagram
SDA
SDA
SCL
Baud Rate Generator
2
SCL
SSPADD<6:0>
C mode fully implements all master and slave functions (including gen-
Preliminary
7
Read
Read
Appendix A
clock
clock
shift
shift
MSb
MSb
Start and Stop bit
detect / generate
Stop bit detect
Match detect
SSPBUF reg
Match detect
SSPADD reg
SSPBUF reg
SSPADD reg
SSPSR reg
SSPSR reg
Start and
gives an overview of the I
LSb
LSb
Write
Write
data bus
data bus
Internal
Internal
(SSPSTAT reg)
(SSPSTAT reg)
and Set SSPIF
Set/Clear S bit
Clear/Set P bit
Address Match
Address Match
Set, Reset
S, P bits
and
1997 Microchip Technology Inc.
2
C bus specification.
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