DSPIC30F6012AT-30I/PT Microchip Technology, DSPIC30F6012AT-30I/PT Datasheet - Page 59
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DSPIC30F6012AT-30I/PT
Manufacturer Part Number
DSPIC30F6012AT-30I/PT
Description
IC DSPIC MCU/DSP 144K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F6011A-30IPT.pdf
(234 pages)
4.DSPIC30F6011A-30IPT.pdf
(8 pages)
5.DSPIC30F6011A-30IPT.pdf
(10 pages)
6.DSPIC30F6011A-30IPT.pdf
(6 pages)
7.DSPIC30F6011A-30IPT.pdf
(8 pages)
8.DSPIC30F6011A-30IPT.pdf
(16 pages)
Specifications of DSPIC30F6012AT-30I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
For Use With
AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6012AT-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F6012AT-30I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
7.3
To write an EEPROM data location, the following
sequence must be followed:
1.
2.
3.
EXAMPLE 7-4:
© 2011 Microchip Technology Inc.
; Point to data memory
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
; Operate key to allow write operation
; Write cycle will complete in 2 ms. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete
Erase data EEPROM word.
a)
b)
c)
d)
e)
f)
g)
h)
Write data word into data EEPROM write
latches.
Program 1 data word into data EEPROM.
a)
b)
c)
d)
e)
f)
g)
MOV
MOV
MOV
MOV
TBLWTL
MOV
MOV
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
Writing to the Data EEPROM
Select word, data EEPROM erase and set
WREN bit in NVMCON register.
Write address of word to be erased into
NVMADR.
Enable NVM interrupt (optional).
Write 0x55 to NVMKEY.
Write 0xAA to NVMKEY.
Set the WR bit. This will begin erase cycle.
Either poll NVMIF bit or wait for NVMIF
interrupt.
The WR bit is cleared when the erase cycle
ends.
Select word, data EEPROM program and
set WREN bit in NVMCON register.
Enable NVM write done interrupt (optional).
Write 0x55 to NVMKEY.
Write 0xAA to NVMKEY.
Set the WR bit. This will begin program
cycle.
Either poll NVMIF bit or wait for NVM
interrupt.
The WR bit is cleared when the write cycle
ends.
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
W1
#LOW(WORD),W2
W2
#0x4004,W0
W0
#5
#0x55,W0
W0
#0xAA,W1
W1
NVMCON,#WR
DATA EEPROM WORD WRITE
,
,
,
,
,
dsPIC30F6011A/6012A/6013A/6014A
TBLPAG
[ W0]
NVMCON
NVMKEY
NVMKEY
; Init pointer
; Get data
; Write data
; Block all interrupts with priority <7 for
; next 5 instructions
; Write the 0x55 key
; Write the 0xAA key
; Initiate program sequence
The write will not initiate if the above sequence is not
exactly followed (write 0x55 to NVMKEY, write 0xAA to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution. The WREN bit should be kept clear at all times
except when updating the EEPROM. The WREN bit is
not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the Non-Volatile Memory
Write Complete Interrupt Flag bit (NVMIF) is set. The
user may either enable this interrupt or poll this bit.
NVMIF must be cleared by software.
7.3.1
Once the user has erased the word to be programmed,
then a table write instruction is used to write one write
latch, as shown in
WRITING A WORD OF DATA
EEPROM
Example
7-4.
DS70143E-page 59