PIC18F2553-I/SP Microchip Technology, PIC18F2553-I/SP Datasheet - Page 20
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PIC18F2553-I/SP
Manufacturer Part Number
PIC18F2553-I/SP
Description
IC PIC MCU FLASH 16KX16 28SDIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2458-ISO.pdf
(46 pages)
3.PIC18F2458-ISO.pdf
(6 pages)
4.PIC18F2458-ISO.pdf
(6 pages)
5.PIC18F2458-ISO.pdf
(6 pages)
Specifications of PIC18F2553-I/SP
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
24
Eeprom Memory Size
256Byte
Ram Memory Size
2KB
Cpu Speed
48MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
MSSP, I2C, SPI, EUSART, CCP, ECCP
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM163025, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 10 Channel
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
5 V
A/d Bit Size
12 bit
A/d Channels Available
10
Height
3.3 mm
Length
34.67 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
7.24 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM163025 - PIC DEM FULL SPEED USB DEMO BRD
Lead Free Status / Rohs Status
Details
PIC18F2XXX/4XXX FAMILY
3.3
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair: EEADRH:EEADR) and
a data latch (EEDATA). Data EEPROM is written by
loading EEADRH:EEADR with the desired memory
location, EEDATA, with the data to be written and initi-
ating a memory write by appropriately configuring the
EECON1 register. A byte write automatically erases the
location and writes the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1).
The write begins on the falling edge of the 4th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
FIGURE 3-7:
DS39622L-page 20
PIC18F2410
PIC18F2450
PIC18F2510
PIC18F2515
PIC18F2610
Note:
PGC
PGD
Poll WR bit
Data EEPROM Programming
4-Bit Command
1
0
Data EEPROM programming is not
available on the the following devices:
2
0
3
0
4
0
PGC
PGD
P5
DATA EEPROM WRITE TIMING
BSF EECON1, WR
1
4-Bit Command
PIC18F4410
PIC18F4450
PIC18F4510
PIC18F4515
PIC18F4610
2
1
0
2
0
15 16
3
0
4
0
P5A
P5
MOVF EECON1, W, 0
1
2
PGD = Input
PGD = Input
15 16
P5A
4-Bit Command
1
Poll WR bit, Repeat until Clear
0
After the programming sequence terminates, PGC must
still be held low for the time specified by Parameter P10
to allow high-voltage discharge of the memory array.
FIGURE 3-6:
2
0
3
0
P11A
(see below)
4
0
P5
MOVWF TABLAT
1
No
2
15 16
PROGRAM DATA FLOW
Enable Write
Set Address
Start Write
Sequence
2010 Microchip Technology Inc.
Set Data
Done?
WR bit
clear?
Done
Start
P5A
Yes
Yes
(see Figure 4-4)
PGD = Output
Shift Out Data
No
P10
16-Bit Data
Payload
1
n
2
n