PIC16LC774/P Microchip Technology, PIC16LC774/P Datasheet - Page 90
![IC MCU OTP 4KX14 A/D PWM 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC16LC774/P
Manufacturer Part Number
PIC16LC774/P
Description
IC MCU OTP 4KX14 A/D PWM 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC774/P
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16LC774-04/P
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PIC16C77X
8.2.18
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ’1’ on SDA by letting SDA float high and
another master asserts a ’0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ’1’ and the data sampled on the SDA pin = ’0’,
then a bus collision has taken place. The master will
set the Bus Collision Interrupt Flag, BCLIF and reset
the I
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision interrupt service routine, and if the I
bus is free, the user can resume communication by
asserting a START condition.
FIGURE 8-34: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
DS30275A-page 90
SDA
SCL
BCLIF
2
C port to its IDLE state.
MULTI -MASTER COMMUNICATION, BUS
COLLISION, AND BUS ARBITRATION
Data changes
while SCL = 0
(Figure
8-34).
Advance Information
SDA released
by master
2
C
SDA line pulled low
by another source
If a START, Repeated Start, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision interrupt service routine, and
if the I
tion by asserting a START condition.
The Master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when bus collision occurred.
In multi-master mode, the interrupt generation on the
detection of start and stop conditions allows the deter-
mination of when the bus is free. Control of the I
can be taken when the P bit is set in the SSPSTAT reg-
ister, or the bus is idle and the S and P bits are cleared.
2
C bus is free, the user can resume communica-
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
Bus collision has occurred.
Set bus collision
interrupt.
1999 Microchip Technology Inc.
2
C bus
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