AT90USB1287-AUR Atmel, AT90USB1287-AUR Datasheet - Page 99
AT90USB1287-AUR
Manufacturer Part Number
AT90USB1287-AUR
Description
MCU AVR 128K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet
1.AT90USB646-MU.pdf
(461 pages)
Specifications of AT90USB1287-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT90USBx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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12.4
7593K–AVR–11/09
General Timer/Counter Control Register – GTCCR
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 2. Prescaler for synchronous Timer/Counters
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-
ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are
halted and can be configured to the same value without the risk of one of them advancing during
configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared
by hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters
When this bit is one, Timer/Counter0 and Timer/Counter1 and Timer/Counter3 prescaler will be
Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note
that Timer/Counter0, Timer/Counter1 and Timer/Counter3 share the same prescaler and a reset
of this prescaler will affect all timers.
Bit
Read/Write
Initial Value
PSR10
clk
CSn0
CSn1
CSn2
Tn
Tn
I/O
Synchronization
Synchronization
7
TSM
R/W
0
6
–
R
0
ExtClk
< f
5
–
R
0
TIMER/COUNTERn CLOCK SOURCE
clk_I/O
/2) given a 50/50% duty cycle. Since the edge detector uses
4
–
R
0
clk
Clear
Tn
3
–
R
0
2
–
R
0
CSn0
CSn1
CSn2
1
PSRA-
SY
R/W
0
AT90USB64/128
TIMER/COUNTERn CLOCK SOURCE
0
PSRSY
NC
R/W
0
clk
Tn
GTCCR
clk_I/O
/2.5.
99
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