AT91SAM7XC256B-AU-999 Atmel, AT91SAM7XC256B-AU-999 Datasheet
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AT91SAM7XC256B-AU-999
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AT91SAM7XC256B-AU-999 Summary of contents
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... Counter May Be Stopped While the Processor is in Debug State or in Idle Mode ® ® Thumb Processor Product Description AT91SAM7XC512 AT91SAM7XC258 AT91SAM7XC128 Summary NOTE: This is a summary document. The complete document is available under NDA. For more information, please contact your local Atmel sales office. 6209DS–ATARM–17-Feb-09 ...
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... Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • One Four-channel 16-bit Power Width Modulation Controller (PWMC) • One Two-wire Interface (TWI) – Master Mode Support Only, All Two-wire Atmel EEPROMs and I • One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os ™ • ...
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Fully Static Operation MHz at 1.65V and 85⋅ C Worst Case Conditions • Available in 100-lead LQFP Green and 100-ball TFBGA Green Packages 6209DS–ATARM–17-Feb-09 AT91SAM7XC512/256/128 Preliminary 3 ...
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... Description Atmel's AT91SAM7XC512/256/128 is a member of a series of highly integrated Flash microcon- trollers based on the 32-bit ARM RISC processor. It features 512/256/128 Kbyte high-speed Flash and 128/64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, a CAN controller, an AES 128 Encryption accelerator and a Triple Data Encryption System. A complete set of system functions minimizes the number of external components ...
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AT91SAM7XC512/256/128 Block Diagram Figure 2-1. JTAGSEL IRQ0-IRQ1 PCK0-PCK3 VDDCORE VDDFLASH VDDCORE SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK 6209DS–ATARM–17-Feb-09 AT91SAM7XC512/256/128 Preliminary AT91SAM7XC512/256/128 Block Diagram TDI TDO ICE JTAG TMS SCAN TCK System ...
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Signal Description Table 3-1. Signal Description List Signal Name Function Voltage Regulator and ADC Power VDDIN Supply Input VDDOUT Voltage Regulator Output VDDFLASH Flash and USB Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL ...
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Table 3-1. Signal Description List (Continued) Signal Name Function DDM USB Device Port Data - DDP USB Device Port Data + SCK0 - SCK1 Serial Clock TXD0 - TXD1 Transmit Data RXD0 - RXD1 Receive Data RTS0 - RTS1 Request ...
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Table 3-1. Signal Description List (Continued) Signal Name Function AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN1 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming Ready PGMNVALID Data Direction PGMNOE Programming Read PGMCK ...
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Package The AT91SAM7XC512/256/128 is available in 100-lead LQFP Green and 100-ball TFBGA RoHS-compliant packages. 4.1 100-lead LQFP Package Outline Figure 4-1 tion is given in the Mechanical Characteristics section of the full datasheet. Figure 4-1. 6209DS–ATARM–17-Feb-09 AT91SAM7XC512/256/128 Preliminary shows ...
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LQFP Pinout Table 4-1. Pinout in 100-lead LQFP Package 1 ADVREF 26 2 GND 27 3 AD4 28 4 AD5 29 5 AD6 30 6 AD7 31 7 VDDOUT 32 8 VDDIN 33 9 PB27/AD0 34 10 PB28/AD1 ...
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TFBGA Package Outline Figure 4-2 description is given in the Mechanical Characteristics section of the full datasheet. Figure 4-2. 4.4 100-ball TFBGA Pinout Table 4-2. Pinout in 100-ball TFBGA Package Pin Signal Name Pin A1 PA22/PGMD10 C6 A2 ...
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Power Considerations 5.1 Power Supplies The AT91SAM7XC512/256/128 has six types of power supply pins and integrates a voltage reg- ulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN ...
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Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 ...
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I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven VDDIO, ...
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I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is ...
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Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM – Thumb • Three-stage pipeline architecture – Instruction ...
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Embedded Flash Controller – Embedded Flash interface three programmable wait states – Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and ...
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Memory 8.1 AT91SAM7XC512 • 512 Kbytes of dual-plane Flash Memory – 2 contiguous banks of 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including ...
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Figure 8-1. AT91SAM7XC512/256/128 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256 MBytes 0xFFFF FFFF 6209DS–ATARM–17-Feb-09 AT91SAM7XC512/256/128 Preliminary Internal ...
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Memory Mapping 8.4.1 Internal RAM • The AT91SAM7XC512 embeds a high-speed 128-Kbyte SRAM bank. • The AT91SAM7XC256 embeds a high-speed 64-Kbyte SRAM bank. • The AT91SAM7XC128 embeds a high-speed 32-Kbyte SRAM bank. After reset and until the Remap Command ...
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Figure 8-3. 8.5 Embedded Flash 8.5.1 Flash Overview • The Flash of the AT91SAM7XC512 is organized in two banks (dual plane) 0f 1254 pages of 256 bytes. The 524, 288 bytes are organized in 32-bit words. • The Flash of ...
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One EFC is embedded in the AT91SAM7XC256/128 to control the single plane of 256/128 KBytes. 8.5.3 Lock Regions 8.5.3.1 AT91SAM7XC512 Two Embedded ...
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Flash Programming Interface, is forbidden. This ensures the confidentiality of the code pro- grammed in the Flash. This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User Interface. Disabling the security bit can ...
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Communication via the USB Device Port is limited to an 18.432 MHz crystal. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped at address 0x0 when the ...
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System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and ...
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Figure 9-1. NRST XIN XOUT PLLRC PA0-PA30 PB0-PB30 AT91SAM7XC512/256/128 Preliminary 26 System Controller Block Diagram System Controller irq0-irq1 Advanced fiq Interrupt Controller periph_irq[2..19] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug Interval periph_nreset ...
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Reset Controller • Based on one power-on reset cell and one brownout detector • Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset • Controls the internal resets and the NRST pin ...
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Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between 3 and 20 ...
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Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: • the Processor Clock PCK • the Master Clock MCK • the USB Clock UDPCK • all the peripheral clocks, independently controllable • four programmable ...
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Higher priority interrupts can be served during service of lower priority interrupt • Vectoring – Optimizes interrupt service routine branch and execution – One 32-bit vector register per interrupt source – Interrupt vector register reads the corresponding current interrupt ...
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Programmable 16-bit prescaler for SLCK accuracy compensation 9.9 PIO Controllers • Two PIO Controllers, each controlling 31 I/O lines • Fully programmable through set/clear registers • Multiplexing of two peripheral functions per I/O line • For each I/O line ...
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Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 MBytes of address space between 0xF000 0000 and 0xFFFE FFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in 10.2 ...
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Peripheral Multiplexing on PIO Lines The AT91SAM7XC512/256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral ...
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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 RXD0 PA1 TXD0 PA2 SCK0 PA3 RTS0 PA4 CTS0 PA5 RXD1 PA6 TXD1 PA7 SCK1 PA8 RTS1 PA9 CTS1 PA10 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 ETXCK/EREFCK PB1 ETXEN PB2 ETX0 PB3 ETX1 PB4 ECRS PB5 ERX0 PB6 ERX1 PB7 ERXER PB8 EMDC PB9 EMDIO PB10 ...
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Ethernet MAC • DMA Master on Receive and Transmit Channels • Compatible with IEEE Standard 802.3 • 10 and 100 Mbit/s operation • Full- and half-duplex operation • Statistics Counter Registers • MII/RMII interface to the physical layer • ...
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Two-wire Interface • Master Mode only • Compatibility with I • One, two or three bytes internal address registers for easy Serial Memory access • 7-bit or 10-bit slave addressing • Sequential read/write operations 10.9 USART • Programmable Baud ...
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Timer Counter • Three 16-bit Timer Counter Channels – Two output compare or one input capture per channel • Wide range of functions including: – Frequency measurement – Event counting – Interval measurement – Pulse generation – Delay timing ...
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USB Device Port • USB V2.0 full-speed compliant,12 Mbits per second • Embedded USB V2.0 full-speed transceiver • Embedded 1352-byte dual-port RAM for endpoints • Six endpoints – Endpoint 0: 8 bytes – Endpoint 1 and 2: 64 bytes ...
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Counter (CTR) • 8-, 16-, 32-, 64- and 128-bit Data Sizes Possible in CFB Mode • Last Output Data Mode allowing Message Authentication Code (MAC) generation • Hardware Countermeasures against Differential Power Analysis attacks • Connection to PDC Channel ...
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Automatic wakeup on trigger and back to sleep mode after conversions of all • Four of eight analog inputs shared with digital signals 6209DS–ATARM–17-Feb-09 AT91SAM7XC512/256/128 Preliminary enabled channels 41 ...
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Package Drawings Figure 11-1. LQFP Package Drawing AT91SAM7XC512/256/128 Preliminary 42 6209DS–ATARM–17-Feb-09 ...
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Table 11-1. Symbol θ1 θ2 θ aaa bbb ccc ddd 6209DS–ATARM–17-Feb-09 AT91SAM7XC512/256/128 Preliminary 100-lead LQFP Package Dimensions Millimeter Min Nom Max 1.60 ...
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Figure 11-2. 100-TFBGA Package Drawing All dimensions are in mm AT91SAM7XC512/256/128 Preliminary 44 6209DS–ATARM–17-Feb-09 ...
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... MLR A Ordering Code MLR B Ordering Code AT91SAM7XC512-AU AT91SAM7XC512-CU AT91SAM7XC256-AU AT91SAM7XC256B-AU AT91SAM7XC256-CU AT91SAM7XC256B-CU AT91SAM7XC128-AU AT91SAM7XC128B-AU AT91SAM7XC128-CU AT91SAM7XC128B-CU 13. Export Regulations Statement These commodities, technology or software will be exported from France and the applicable Export Administration Regulations will apply. French, United States and other relevant laws, reg- ulations and requirements regarding the export of products may restrict sale, export and re- export of these products ...
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... Added LQFP and TFBGA package drawings System Controller block diagram “Features”, TWI updated to include Atmel TWI compatibility with I “Features”, “Debug Unit (DBGU)” Section 10.8 ”Two-wire Section 10.11 ”Timer Counter”,The TC has Two output compare or one input capture per channel. ...
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