PIC18F442-E/PT Microchip Technology, PIC18F442-E/PT Datasheet - Page 2
![IC MCU CMOS 40MHZ 8K FLSH 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F442-E/PT
Manufacturer Part Number
PIC18F442-E/PT
Description
IC MCU CMOS 40MHZ 8K FLSH 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18F442-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F442-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18FXX2
3. Module: Interrupts
DS80127G-page 2
Note:
Under certain conditions, the use of dual priority
interrupts may cause a program instruction to be
skipped entirely. This has only been observed
when both of the following apply:
• Both high and low interrupts are enabled, and
• A high priority asynchronous interrupt occurs
The event causes the stack to get pushed twice
and will eventually result in an overflow.
Work around
Two possible solutions are presented. Other
solutions may exist.
1. Enable only high priority interrupts for all
2. If it is necessary to use both high and low
Date Codes that pertain to this issue:
All engineering and production devices.
in the following cycle after any low priority
interrupt.
sources, both synchronous and asynchronous.
interrupt priorities:
• Assign asynchronous interrupts as low
• Assign synchronous interrupts to both high
priority only.
and low priority, as needed.
This does not apply to the INT0 (external)
interrupt as it is always configured as a
high priority interrupt.
4. Module: Core (Program Memory Space)
5. Module: Core (Program Memory Space)
Note:
Performing table read operations above the user
program
1FFFFFh) may yield erroneous results at the
extreme low end of the device’s rated temperature
range (-40°C).
This applies specifically to addresses above
1FFFFFh,
(200000h-200007h),
(300000h-30000Dh), and the device ID locations
(3FFFFEh and 3FFFFFh). User program memory
is unaffected.
Work around
Three possible work arounds are presented. Other
solutions may exist.
1. Do not perform table read operations on areas
2. Insert NOP instructions (specifically, literal
Date Codes that pertain to this issue:
All engineering and production devices.
Under certain conditions, the execution of a table
read instruction may yield erroneous results. This
has been observed when a table read instruction
and its read destination, as indicated by the Table
Pointer registers, are on opposite sides of the
4000h program memory address boundary.
This behavior has not been observed when the
instruction and its target both occur strictly within
the same half of the program memory space.
Work around
Insert a data word of value FFFFh immediately fol-
lowing any table read instruction. This behaves as
a NOP instruction when executed. Using the actual
NOP instruction instead of a literal FFFFh may not
have the same results.
This is a recommended solution. Others may exist.
Date Codes that pertain to this issue:
All engineering samples and devices with date
codes up to and including 0252 (Year 2002, Work
Week 52).
above the user memory space at -40°C.
FFFFh) around any table read instructions.
The suggested optimal number is 4 instruc-
tions before and 8 instructions after each table
read. This may vary depending upon the
particular application, and should be optimized
by the user.
This issue applies only to PIC18F252
and PIC18F452 devices with 32K words of
Flash program memory. PIC18F242 and
PIC18F442 devices are not affected.
memory
including
© 2005 Microchip Technology Inc.
space
the
the
configuration
user
(addresses
ID
locations
bytes
over