AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 81
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AT32UC3A364-ALUT
Manufacturer Part Number
AT32UC3A364-ALUT
Description
IC MCU 64KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A364-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
110
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
13.1.7
13.1.8
13.1.9
13.2
13.2.1
32072C–AVR32–2010/03
Rev. E
AES
HMATRIX
TWIM
General
1. URAD (Unspecified Register Access Detection Status) does not detect read accesses
1. In the HMATRIX PRAS and PRBS registers MxPR fields are only two bits
1. TWIM SR.IDLE goes high immediately when NAK is received
1. 3.3V supply monitor is not available on revE.
2. Service access bus (SAB) can not access DMACA registers.
3. Increased Power Consumption in VDDIO in sleep modes.
Fix/workaround:
Disable and then enable the peripheral after the transfer error.
to the write-only KEYW[5..8]R registers
Fix/Workaround
None.
In the HMATRIX PRAS and PRBS registers MxPR fields are only two bits wide, instead of
four bits. The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
3.3V supply monitor is not available on revE.
Fix/workaround
None.
Workaround
None.
If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis-
abled, this will lead to an increased power consumption in VDDIO.
Workaround
Disable OSC0 manually through the Power Manager (PM) before going to any sleep modes
where the OSC0 is disabled automatically, or pull down or up XIN0 or XOUT0 with 1Mohm
resistor.
AT32UC3A3/A4
81