PIC18F458T-I/PT Microchip Technology, PIC18F458T-I/PT Datasheet - Page 69
PIC18F458T-I/PT
Manufacturer Part Number
PIC18F458T-I/PT
Description
IC MCU FLASH 16KX16 W/CAN 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18LF242-ISO.pdf
(36 pages)
3.PIC18F248-ISO.pdf
(402 pages)
4.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18F458T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F458T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18LF242-ISO PDF datasheet #2
- PIC18F248-ISO PDF datasheet #3
- PIC18F248-ISO PDF datasheet #4
- Current page: 69 of 402
- Download datasheet (7Mb)
REGISTER 6-1:
© 2006 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EECON1: EEPROM CONTROL REGISTER 1
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access program Flash memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EE or Configuration Select bit
1 = Access Configuration registers
0 = Access program Flash or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write only
WRERR: Write Error Flag bit
1 = A write operation is prematurely terminated
0 = The write operation completed
WREN: Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM or Flash memory
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
-n = Value at POR
EEPGD
R/W-x
Note:
(cleared by completion of erase operation)
(any MCLR or any WDT Reset during self-timed programming in normal operation)
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
CFGS
R/W-x
W = Writable bit
‘1’ = Bit is set
U-0
—
R/W-0
FREE
S = Settable bit
‘0’ = Bit is cleared
WRERR
R/W-x
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
WREN
R/W-0
PIC18FXX8
R/S-0
WR
DS41159E-page 67
R/S-0
RD
bit 0
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