PIC16F874-04/PT Microchip Technology, PIC16F874-04/PT Datasheet - Page 290
![IC MCU FLASH 4KX14 EE 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC16F874-04/PT
Manufacturer Part Number
PIC16F874-04/PT
Description
IC MCU FLASH 4KX14 EE 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F873-04SO.pdf
(218 pages)
4.PIC16F873-04SO.pdf
(5 pages)
5.PIC16F873-04SO.pdf
(5 pages)
Specifications of PIC16F874-04/PT
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Oscillator Type
External
Core Processor
PIC
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC16F
No. Of I/o's
33
Eeprom Memory Size
128Byte
Ram Memory Size
192Byte
Cpu Speed
4MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F874-04/PT
Manufacturer:
MICROCHIP
Quantity:
4 500
Company:
Part Number:
PIC16F874-04/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F873-04SO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- Current page: 290 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.3.5
17.3.6
DS31017A-page 17-14
Slave Mode
Slave Select Synchronization
In slave mode, the data is transmitted and received as the external clock pulses appear on SCK.
When the last bit is latched, the SSPIF interrupt flag bit is set.
While in slave mode the external clock is supplied by the external clock source on the SCK pin.
This external clock must meet the minimum high and low times as specified in the electrical spec-
ifications.
While in sleep mode, the slave can transmit/receive data. When a byte is receive the device will
wake-up from sleep.
The SS pin allows a synchronous slave mode. The SPI must be in slave mode with SS pin
control enabled (SSPCON1<3:0> = 04h). The pin must not be driven low for the SS pin to
function as an input. The Data Latch must be high. When the SS pin is low, transmission
and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO
pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating
output. External pull-up/ pull-down resistors may be desirable, depending on the application.
When the SPI module resets, the bit counter is forced to 0. This can be done by either by forcing
the SS pin to a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the
SPI needs to operate as a receiver the SDO pin can be configured as an input. This disables
transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot
create a bus conflict.
Note 1: When the SPI is in Slave Mode with SS pin control enabled, (SSPCON<3:0> =
Note 2: If the SPI is used in Slave Mode with CKE is set, then the SS pin control must be
0100) the SPI module will reset if the SS pin is set to V
enabled.
Preliminary
1997 Microchip Technology Inc.
DD
.
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