PIC18LF458-I/P Microchip Technology, PIC18LF458-I/P Datasheet - Page 183

IC MCU CAN FLASH 16K LP 40-DIP

PIC18LF458-I/P

Manufacturer Part Number
PIC18LF458-I/P
Description
IC MCU CAN FLASH 16K LP 40-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF458-I/P

Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
33
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF458-I/P
Manufacturer:
MICROCHIP
Quantity:
2 100
Part Number:
PIC18LF458-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18LF458-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
17.4.17.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 17-31:
FIGURE 17-32:
© 2006 Microchip Technology Inc.
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
SDA
SCL
PEN
BCLIF
P
SSPIF
SSPIF
BCLIF
SDA
PEN
SCL
Bus Collision During a Stop
Condition
P
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
Assert SDA
T
SDA asserted low
BRG
T
BRG
T
BRG
T
BRG
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 17-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 17-32).
SCL goes low before SDA goes high,
set BCLIF
T
BRG
T
BRG
PIC18FXX8
‘0’
‘0’
DS41159E-page 181
SDA sampled
low after T
set BCLIF
‘0’
‘0’
BRG
,

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