PIC18F2515-I/SP Microchip Technology, PIC18F2515-I/SP Datasheet - Page 71
![IC MCU FLASH 24KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2515-I/SP
Manufacturer Part Number
PIC18F2515-I/SP
Description
IC MCU FLASH 24KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18LF2410-ISO.pdf
(376 pages)
3.PIC18LF2410-ISO.pdf
(8 pages)
4.PIC18F2515-ISO.pdf
(16 pages)
5.PIC18F2515-ISO.pdf
(6 pages)
6.PIC18F2515-ISO.pdf
(8 pages)
Specifications of PIC18F2515-I/SP
Core Size
8-Bit
Program Memory Size
48KB (24K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Ram Memory Size
3968Byte
Cpu Speed
40MHz
No. Of Timers
4
Interface
I2C, SPI, USART
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2515-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18LF2410-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18F2515-ISO PDF datasheet #4
- PIC18F2515-ISO PDF datasheet #5
- PIC18F2515-ISO PDF datasheet #6
- Current page: 71 of 376
- Download datasheet (7Mb)
The PLUSW register can be used to implement a form
of indexed addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
5.4.3.3
Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For exam-
ple, using an FSR to point to one of the virtual registers
will not result in successful operations. As a specific
case, assume that FSR0H:FSR0L contains FE7h, the
address of INDF1. Attempts to read the value of the
INDF1 using INDF0 as an operand will return 00h.
Attempts to write to INDF1 using INDF0 as the operand
will result in a NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses indirect addressing.
Similarly, operations by indirect addressing are gener-
ally permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
5.5
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifi-
cally, the use of the Access Bank for many of the core
PIC18 instructions is different; this is due to the
introduction of a new addressing mode for the data
memory space.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing
with FSR0 and FSR1 also remain unchanged.
© 2009 Microchip Technology Inc.
Data Memory and the Extended
Instruction Set
Operations by FSRs on FSRs
5.5.1
Enabling the PIC18 extended instruction set changes
the behavior of indirect addressing using the FSR2
register pair within access RAM. Under the proper
conditions, instructions that use the Access Bank – that
is, most bit-oriented and byte-oriented instructions –
can invoke a form of indexed addressing using an
offset specified in the instruction. This special address-
ing mode is known as Indexed Addressing with Literal
Offset, or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
• The file address argument is less than or equal to
Under these conditions, the file address of the instruc-
tion is not interpreted as the lower byte of an address
(used with the BSR in direct addressing), or as an 8-bit
address in the Access Bank. Instead, the value is
interpreted as an offset value to an Address Pointer,
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
5.5.2
Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed Literal
Offset Addressing mode. This includes all byte-oriented
and bit-oriented instructions, or almost one-half of the
standard PIC18 instruction set. Instructions that only use
Inherent or Literal Addressing modes are unaffected.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’), or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the
different possible addressing modes when the
extended instruction set is enabled is shown in
Figure 5-10.
Those who desire to use bit-oriented or byte-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 23.2.1
“Extended Instruction Syntax”.
and
5Fh.
PIC18F2X1X/4X1X
INDEXED ADDRESSING WITH
LITERAL OFFSET
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
DS39636D-page 73
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