AT91SAM7S321-AU Atmel, AT91SAM7S321-AU Datasheet - Page 290
![IC ARM7 MCU FLASH 32K 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT91SAM7S321-AU
Manufacturer Part Number
AT91SAM7S321-AU
Description
IC ARM7 MCU FLASH 32K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91SAM7S16-MU.pdf
(51 pages)
2.AT91SAM7S16-MU.pdf
(779 pages)
3.AT91SAM7S321-AU.pdf
(600 pages)
Specifications of AT91SAM7S321-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, I2S, SPI, SSC, TWI, UART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
32
Number Of Timers
10 bit
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxx
No. Of I/o's
32
Ram Memory Size
8KB
Cpu Speed
55MHz
No. Of Timers
3
Rohs Compliant
Yes
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Figure 29-5. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 29-6. Master Write with One Byte Internal Address and Multiple Data Bytes
Figure 29-7. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
290
TXCOMP
TWD
TWD
TWD
TWD
TWD
TWD
TXRDY
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
AT91SAM7S Series Preliminary
S
S
S
S
Write THR
Write THR
DADR
DADR
DADR
DADR
DADR
DADR
DADR
W
W
W
sets the NAK bit in the status register if the slave does not acknowledge the byte. As with the
other status bits, an interrupt can be generated if enabled in the interrupt enable register
(TWI_IER). After writing in the transmit-holding register (TWI_THR), setting the START bit in the
control register starts the transmission. The data is shifted in the internal shifter and when an
acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR (see
6
The read sequence begins by setting the START bit. When the RXRDY bit is set in the status
register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY
bit is reset when reading the TWI_RHR.
The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave address).
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR). If the slave device supports only a 7-bit address, IADRSZ must be set to 0. For a
slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the
other slave address bits in the internal address register (TWI_IADR).
W
below). The master generates a stop condition to end the transfer.
W
W
W
A
A
A
A
A
A
A
IADR(23:16)
IADR(15:8)
IADR(7:0)
IADR(7:0)
IADR(23:16)
IADR(15:8)
IADR(7:0)
A
A
A
A
IADR(15:8)
A
A
A
IADR(7:0)
S
DADR
IADR(15:8)
DATA
IADR(7:0)
DATA
A
A
R
Write THR
A
IADR(7:0)
S
A
A
A
A
DADR
IADR(7:0)
P
DATA
DATA
A
DATA
R
S
Write THR
A
A
A
A
N
DADR
DATA
P
DATA
P
DATA
DATA
6175G–ATARM–22-Nov-06
R
N
P
A
N
A
Figure 29-
A
P
P
P
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