PIC16F767-I/SS Microchip Technology, PIC16F767-I/SS Datasheet - Page 187
![IC PIC MCU FLASH 8KX14 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16F767-I/SS
Manufacturer Part Number
PIC16F767-I/SS
Description
IC PIC MCU FLASH 8KX14 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F737-ISP.pdf
(276 pages)
4.PIC16F737-ISP.pdf
(10 pages)
Specifications of PIC16F767-I/SS
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC16F
No. Of I/o's
25
Ram Memory Size
368Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DBF777 - BOARD DAUGHTER ICEPIC3AC164307 - MODULE SKT FOR PM3 28SSOPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F767-I/SS
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F737-ISP PDF datasheet #3
- PIC16F737-ISP PDF datasheet #4
- Current page: 187 of 276
- Download datasheet (6Mb)
15.15.1
External interrupt on the RB0/INT pin is edge-triggered,
either rising if bit INTEDG (OPTION_REG<6>) is set or
falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INT0IF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit, INT0IE (INTCON<4>). Flag bit
INT0IF must be cleared in software in the Interrupt
Service Routine before re-enabling this interrupt. The
INT interrupt can wake-up the processor from Sleep if
bit INT0IE was set prior to going into Sleep. The status
of Global Interrupt Enable bit, GIE, decides whether or
not the processor branches to the interrupt vector
following wake-up. See Section 15.18 “Power-Down
Mode (Sleep)” for details on Sleep mode.
15.15.2
An overflow (FFh
flag bit, TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled
TMR0IE (INTCON<5>), see Section 6.0 “Timer0
Module”.
EXAMPLE 15-1:
2004 Microchip Technology Inc.
MOVWF
SWAPF
CLRF
MOVWF
:
:(ISR)
:
SWAPF
MOVWF
SWAPF
SWAPF
INT INTERRUPT
TMR0 INTERRUPT
W_TEMP
STATUS, W
STATUS
STATUS_TEMP
STATUS_TEMP, W
STATUS
W_TEMP, F
W_TEMP, W
by
00h) in the TMR0 register will set
SAVING STATUS AND W REGISTERS IN RAM
setting/clearing
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Insert user code here
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
enable
bit,
15.15.3
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<4>), see
Section 2.2 “Data Memory Organization”.
15.16 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (i.e., W, Status registers).
Since the upper 16 bytes of each bank are common in
the PIC16F7X7 devices, temporary holding registers,
W_TEMP,
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for
context save and restore. The same code shown in
Example 15-1 can be used.
PORTB INTCON CHANGE
STATUS_TEMP
PIC16F7X7
and
DS30498C-page 185
PCLATH_TEMP,
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