ATMEGA649V-8AU Atmel, ATMEGA649V-8AU Datasheet - Page 331

• Manufacturer Part Number: ATMEGA649V-8AU
• Description: IC AVR MCU FLASH 64K 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA649V-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Cpu Family: ATmega
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 54
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.6
2552K–AVR–04/11
SPI Timing Characteristics
See
Table 28-6.
Note:
Figure 28-4. SPI Interface Timing Requirements (Master Mode)
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 28-4
(Data Output)
(Data Input)
(CPOL = 0)
(CPOL = 1)
1. In SPI Programming mode the minimum SCK high/low period is:
SS high to tri-state
SCK to out high
SCK to SS high
- 2 t
- 3 t
MISO
MOSI
SCK high/low
SS low to SCK
Rise/Fall time
Rise/Fall time
SCK
SCK
SCK high/low
SS low to out
Description
SCK period
SCK period
Out to SCK
SCK to out
SCK to out
SS
SPI Timing Parameters
CLCL
CLCL
Setup
Setup
Hold
Hold
and
for f
for f
Figure 28-5
CK
CK
(1)
< 12MHz
> 12MHz
6
4
MSB
5
MSB
for details.
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
7
20 • t
4 • t
2 • t
ATmega329/3290/649/6490
Min
10
20
t
ck
...
ck
ck
ck
...
See
50% duty cycle
0.5 • t
Table 18-5
Typ
3.6
1.6
10
10
10
10
15
15
10
2
sck
LSB
1
LSB
2
Max
3
8
ns
µs
ns
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