DSPIC33FJ128GP708-E/PT Microchip Technology, DSPIC33FJ128GP708-E/PT Datasheet - Page 13
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
DSPIC33FJ128GP708-E/PT
Manufacturer Part Number
DSPIC33FJ128GP708-E/PT
Description
IC DSPIC MCU/DSP 128K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
3.DSPIC33FJ64GP206-IPT.pdf
(28 pages)
Specifications of DSPIC33FJ128GP708-E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
21. Module: UART
22. Module: UART
23. Module: I
© 2010 Microchip Technology Inc.
The auto-baud feature may not calculate the correct
baud rate when the High Baud Rate Enable bit,
BRGH, is set. With the BRGH bit set, the baud rate
calculation used is the same as BRG = 0.
Work around
If the auto-baud feature is needed, use the Low
Baud Rate mode by clearing the BRGH bit.
Affected Silicon Revisions
With the auto-baud feature selected, the Sync
Break character (0x55) may be loaded into the
FIFO as data.
Work around
To prevent the Sync Break character from being
loaded into the FIFO, load the UxBRG register with
either 0x0000 or 0xFFFF prior to enabling the
auto-baud feature (ABAUD = 1).
Affected Silicon Revisions
Writing to I2CxTRN during a Start bit transmission
generates a write collision, indicated by the
IWCOL bit (I2CxSTAT<7>) being set. In this state,
additional writes to the I2CxTRN register should
be blocked. However, in this condition, the
I2CxTRN register can be written, although
transmissions will not occur until the IWCOL bit is
cleared in software.
Work around
After each write to the I2CxTRN register, read the
IWCOL bit to ensure a collision has not occurred.
If the IWCOL bit is set, it must be cleared in
software, and I2CxTRN register must be rewritten.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
2
C
A4
A4
A4
X
X
X
24. Module: I
25. Module: I
The ACKSTAT bit (I2CxSTAT<15>) only reflects
the received ACK/NACK status for master
transmissions, but not for Slave transmissions. As
a result, a slave cannot use this bit to determine
whether it received an ACK or a NACK from a
master. In future silicon revisions, the ACKSTAT
bit will reflect received ACK/NACK status for both
master and slave transmissions.
Work around
The SDA pin should be connected to any other
available I/O pin on the device. After transmitting a
byte, the slave should poll the SDA line (subject to
a time-out period that is dependent on the
application) to determine whether an ACK (‘0’) or
a NACK (‘1’) was received.
Affected Silicon Revisions
The D_A Status bit (I2CxSTAT<5>) is set on a
slave data reception in the I2CxRCV register, but
is not set on a slave write to the I2CxTRN register.
In future silicon revisions, the D_A bit will be set on
a slave write to the I2CxTRN register.
Work around
Use the D_A Status bit only for determining slave
reception status. Do not use it for determining
slave transmission status.
Affected Silicon Revisions
A2
A2
X
X
A3
A3
X
X
2
2
C
C
A4
A4
X
X
DS80446D-page 13