PIC18F4520-I/PT Microchip Technology, PIC18F4520-I/PT Datasheet - Page 247

• Manufacturer Part Number: PIC18F4520-I/PT
• Description: IC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4520-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: MSSP/SPI/I2C/PSP/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, 53275-917, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.2
The following steps are needed to set up the HLVD
module:
1.
2.
3.
4.
5.
22.3
When the module is enabled, the HLVD comparator
and voltage divider are enabled and will consume static
current. The total current consumption, when enabled,
is specified in electrical specification parameter D022B.
FIGURE 22-2:
© 2008 Microchip Technology Inc.
Write the value to the HLVDL<3:0> bits that
selects the desired HLVD trip point.
Set the VDIRMAG bit to detect high voltage
(VDIRMAG = 1) or low voltage (VDIRMAG = 0).
Enable the HLVD module by setting the
HLVDEN bit.
Clear the HLVD interrupt flag (PIR2<2>), which
may have been set from a previous interrupt.
Enable the HLVD interrupt, if interrupts are
desired, by setting the HLVDIE and GIE bits
(PIE2<2> and INTCON<7>). An interrupt will not
be generated until the IRVST bit is set.
CASE 1:
CASE 2:
Enable HLVD
Enable HLVD
HLVD Setup
Current Consumption
HLVDIF
HLVDIF
IRVST
IRVST
V
V
DD
DD
LOW-VOLTAGE DETECT OPERATION (VDIRMAG =
Internal Reference is Stable
Advance Information
PIC18F2420/2520/4420/4520
Internal Reference is Stable
T
T
IRVST
IRVST
HLVDIF may not be set
HLVDIF cleared in software,
HLVDIF remains set since HLVD condition still exists
Depending on the application, the HLVD module does
not need to be operating constantly. To decrease the
current requirements, the HLVD circuitry may only
need to be enabled for short periods where the voltage
is checked. After doing the check, the HLVD module
may be disabled.
22.4
The internal reference voltage of the HLVD module,
specified in electrical specification parameter D420,
may be used by other internal circuitry, such as the
programmable Brown-out Reset. If the HLVD or other
circuits using the voltage reference are disabled to
lower the device’s current consumption, the reference
voltage circuit will require time to become stable before
a low or high-voltage condition can be reliably
detected. This start-up time, T
is independent of device clock speed. It is specified in
electrical specification parameter 36.
The HLVD interrupt flag is not enabled until T
expired and a stable reference voltage is reached. For
this reason, brief excursions beyond the set point may
not be detected during this interval (refer to Figure 22-2
or Figure 22-3).
HLVD Start-up Time
HLVDIF Cleared in Software
0
)
HLVDIF Cleared in Software
IRVST
V
V
DS39631E-page 245
, is an interval that
LVD
LVD
IRVST
has