PIC16F876A-I/ML Microchip Technology, PIC16F876A-I/ML Datasheet - Page 106

• Manufacturer Part Number: PIC16F876A-I/ML
• Description: IC MCU FLASH 8KX14 A/D 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F876A-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Data Rom Size: 256 B
• Height: 0.88 mm
• Length: 6 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 6 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F87XA
9.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (T
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for T
pulled low. Following this, the ACKEN bit is automatically
cleared, the baud rate generator is turned off and the
MSSP module then goes into Idle mode (Figure 9-23).
9.4.12.1
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-23:
FIGURE 9-24:
DS39582B-page 104
ACKNOWLEDGE SEQUENCE
TIMING
Note: T
Note: T
WCOL Status Flag
SCL
SDA
SSPIF
Sequence
Acknowledge sequence starts here,
SDA
SCL
Write to SSPCON2,
BRG
Falling edge of
9th clock
BRG
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
= one Baud Rate Generator period.
Set SSPIF at the end
of receive
= one Baud Rate Generator period.
ACK
ACKEN = 1, ACKDT = 0
BRG
set PEN
Enable
. The SCL pin is then
write to SSPCON2
bit,
T
8
T
D0
BRG
BRG
SDA asserted low before rising edge of clock
to setup Stop condition
ACKEN
BRG
T
SCL brought high after T
BRG
)
Cleared in
software
T
BRG
P
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
ACK
T
BRG
9.4.13
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the Baud Rate Generator is reloaded and
counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
T
SDA pin will be deasserted. When the SDA pin is sam-
pled high while SCL is high, the P bit (SSPSTAT<4>) is
set. A T
bit is set (Figure 9-24).
9.4.13.1
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
BRG
T
BRG
9
PEN bit (SSPCON2<2>) is cleared by
Set SSPIF at the end
of Acknowledge sequence
(Baud Rate Generator rollover count) later, the
hardware and the SSPIF bit is set
BRG
BRG
BRG
, followed by SDA = 1 for T
STOP CONDITION TIMING
later, the PEN bit is cleared and the SSPIF
ACKEN automatically cleared
WCOL Status Flag
Cleared in
software
 2003 Microchip Technology Inc.
BRG