PIC16F767-I/SO Microchip Technology, PIC16F767-I/SO Datasheet - Page 28

• Manufacturer Part Number: PIC16F767-I/SO
• Description: IC PIC MCU FLASH 8KX14 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: AUSART, CCP, I2C, MSSP, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILI3DBF777 - BOARD DAUGHTER ICEPIC3
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F7X7
2.2.2.6
The PIE2 register contains the individual enable bits for
the CCP2 and CCP3 peripheral interrupts.
REGISTER 2-6:
DS30498C-page 26
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIE2 Register
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
bit 7
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = LVD interrupt is enabled
0 = LVD interrupt is disabled
Unimplemented: Read as ‘0’
BCLIE: Bus Collision Interrupt Enable bit
1 = Enable bus collision interrupt in the SSP when configured for I
0 = Disable bus collision interrupt in the SSP when configured for I
Unimplemented: Read as ‘0’
CCP3IE: CCP3 Interrupt Enable bit
1 = Enables the CCP3 interrupt
0 = Disables the CCP3 interrupt
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit
-n = Value at POR
OSFIE
R/W-0
R/W-0
CMIE
R/W-0
LVDIE
W = Writable bit
‘1’ = Bit is set
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
BCLIE
U-0
 2004 Microchip Technology Inc.
—
2
2
C Master mode
C Master mode
x = Bit is unknown
CCP3IE
R/W-0
CCP2IE
R/W-0
bit 0