ATMEGA32U4-MU Atmel, ATMEGA32U4-MU Datasheet - Page 159
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ATMEGA32U4-MU
Manufacturer Part Number
ATMEGA32U4-MU
Description
MCU AVR 32K FLASH 16MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U4-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Package
44QFN EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
26
Interface Type
EBI/I2S/SPI/TWI/USART/USB
On-chip Adc
12-chx10-bit
Number Of Timers
5
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA32U4-16MU
ATMEGA32U4-16MU
ATMEGA32U4-16MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
- Current page: 159 of 433
- Download datasheet (9Mb)
15.11 Accessing 10-Bit Registers
7766F–AVR–11/10
If 10-bit values are written to the TCNTn and OCRnA/B/C/D registers, the 10-bit registers can be
byte accessed by the AVR CPU via the 8-bit data bus using two read or write operations. The
10-bit registers have a common 2-bit Timer/Counter4 High Byte Register (TC4H) that is used for
temporary storing of the two MSBs of the 10-bit access. The same TC4H register is shared
between all 10-bit registers. Accessing the low byte triggers the 10-bit read or write operation.
When the low byte of a 10-bit register is written by the CPU, the high byte stored in the TC4H
register, and the low byte written are both copied into the 10-bit register in the same clock cycle.
When the low byte of a 10-bit register is read by the CPU, the high byte of the 10-bit register is
copied into the TC4H register in the same clock cycle as the low byte is read.
To do a 10-bit write, the high byte must be written to the TC4H register before the low byte is
written. For a 10-bit read, the low byte must be read before the high byte.
The following code examples show how to access the 10-bit timer registers assuming that no
interrupts updates the TC4H register. The same principle can be used directly for accessing the
OCRnA/B/C/C/D registers.
Note:
The assembly code example returns the TCNTn value in the r17:r16 register pair.
Assembly Code Example
C Code Example
unsigned int i;
...
/* Set TCNTn to 0x01FF */
TCnH = 0x01;
TCNTn = 0xFF;
/* Read TCNTn into i */
i = TCNTn;
i |= ((unsigned int)TCnH << 8);
...
...
; Set TCNTn to 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCnH,r17
out TCNTn,r16
; Read TCNTn into r17:r16
in r16,TCNTn
in r17,TCnH
...
1. The example code assumes that the part specific header file is included.
For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
ATmega16/32U4
159
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