PIC16LC64A-04/PQ Microchip Technology, PIC16LC64A-04/PQ Datasheet - Page 38
![IC MCU OTP 2KX14 PWM 44-MQFP](/photos/6/59/65984/150-44-pqfp_sml.jpg)
PIC16LC64A-04/PQ
Manufacturer Part Number
PIC16LC64A-04/PQ
Description
IC MCU OTP 2KX14 PWM 44-MQFP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheet
1.PIC16LC62A-04SP.pdf
(337 pages)
Specifications of PIC16LC64A-04/PQ
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-MQFP, 44-PQFP
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
33
Number Of Timers
3 bit
Operating Supply Voltage
2.5 V to 6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LC64A-04/PQ
Manufacturer:
MICROCHI
Quantity:
239
Company:
Part Number:
PIC16LC64A-04/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC16C6X
4.2.2.4
This register contains the individual enable bits for the
peripheral interrupts.
FIGURE 4-12: PIE1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 8Ch)
DS30234D-page 38
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
bit7
bit 7-6:
bit 5-4:
bit 3:
bit 2:
bit 1:
bit 0:
RW-0
—
PIE1 REGISTER
Reserved: Always maintain these bits clear.
Unimplemented: Read as '0'
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
R/W-0
—
U-0
—
U-0
—
SSPIE
R/W-0
CCP1IE
R/W-0
TMR2IE
R/W-0
Note:
TMR1IE
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
1997 Microchip Technology Inc.
read as ‘0’
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