DSPIC33FJ64GP204-I/PT Microchip Technology, DSPIC33FJ64GP204-I/PT Datasheet - Page 371

• Manufacturer Part Number: DSPIC33FJ64GP204-I/PT
• Description: IC DSPIC MCU/DSP 64K 44-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GP204-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Embedded Interface Type: ECAN, I2C, SPI, UART
• No. Of I/o's: 35
• Flash Memory Size: 64KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

J
JTAG Boundary Scan Interface ........................................ 287
JTAG Interface .................................................................. 293
M
Memory Organization.......................................................... 29
Microchip Internet Web Site .............................................. 373
Modes of Operation
Modulo Addressing ............................................................. 56
MPLAB ASM30 Assembler, Linker, Librarian ................... 306
MPLAB ICD 2 In-Circuit Debugger ................................... 307
MPLAB ICE 2000 High-Performance Universal
MPLAB Integrated Development Environment
MPLAB PM3 Device Programmer .................................... 307
MPLAB REAL ICE In-Circuit Emulator System................. 307
MPLINK Object Linker/MPLIB Object Librarian ................ 306
N
NVM Module
O
Open-Drain Configuration ................................................. 146
Output Compare ............................................................... 185
P
Packaging ......................................................................... 355
Peripheral Module Disable (PMD) .................................... 144
PICSTART Plus Development Programmer ..................... 308
Pinout I/O Descriptions (table) ............................................ 15
PMD Module
PORTA
PORTB
Power-on Reset (POR) ....................................................... 74
Power-Saving Features .................................................... 143
Program Address Space ..................................................... 29
© 2008 Microchip Technology Inc.
Disable ...................................................................... 211
Initialization ............................................................... 211
Listen All Messages .................................................. 211
Listen Only ................................................................ 211
Loopback .................................................................. 211
Normal Operation...................................................... 211
Applicability ................................................................. 57
Operation Example ..................................................... 56
Start and End Address................................................ 56
W Address Register Selection .................................... 56
In-Circuit Emulator .................................................... 307
Software.................................................................... 305
Register Map............................................................... 53
Details ....................................................................... 356
Marking ..................................................................... 355
Register Map............................................................... 53
Register Map......................................................... 51, 52
Register Map............................................................... 52
Clock Frequency and Switching................................ 143
Construction................................................................ 59
Data Access from Program Memory
Data Access from Program Memory Using
Data Access from, Address Generation...................... 60
Memory Map ............................................................... 29
Table Read Instructions
Visibility Operation ...................................................... 62
Using Program Space Visibility........................... 62
Table Instructions ............................................... 61
TBLRDH ............................................................. 61
TBLRDL .............................................................. 61
Preliminary
Program Memory
R
Reader Response............................................................. 374
Register Map
Registers
Interrupt Vector........................................................... 30
Organization ............................................................... 30
Reset Vector............................................................... 30
CRC............................................................................ 51
Dual Comparator ........................................................ 51
Parallel Master/Slave Port .......................................... 50
Real-Time Clock and Calendar .................................. 51
AD1CHS0 (ADC1 Input Channel 0 Select................ 251
AD1CHS123 (ADC1 Input Channel 1, 2,
AD1CON1 (ADC1 Control 1) .................................... 245
AD1CON2 (ADC1 Control 2) .................................... 247
AD1CON3 (ADC1 Control 3) .................................... 248
AD1CON4 (ADC1 Control 4) .................................... 249
AD1CSSL (ADC1 Input Scan Select Low) ............... 252
AD1PCFGL (ADC1 Port Configuration Low) ............ 252
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer) .......... 221
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer) .......... 222
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer) ........ 222
CiBUFPNT4 (ECAN Filter 12-15 Buffer
CiCFG1 (ECAN Baud Rate Configuration 1)............ 219
CiCFG2 (ECAN Baud Rate Configuration 2)............ 220
CiCTRL1 (ECAN Control 1) ...................................... 212
CiCTRL2 (ECAN Control 2) ...................................... 213
CiEC (ECAN Transmit/Receive Error Count) ........... 219
CiFCTRL (ECAN FIFO Control) ............................... 215
CiFEN1 (ECAN Acceptance Filter Enable)............... 221
CiFIFO (ECAN FIFO Status) .................................... 216
CiFMSKSEL1 (ECAN Filter 7-0 Mask
CiINTE (ECAN Interrupt Enable) .............................. 218
CiINTF (ECAN Interrupt Flag) .................................. 217
CiRXFnEID (ECAN Acceptance Filter n
CiRXFnSID (ECAN Acceptance Filter n
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 228
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 228
CiRXMnEID (ECAN Acceptance Filter
CiRXMnSID (ECAN Acceptance Filter
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 229
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 229
CiTRBnSID (ECAN Buffer n Standard
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 230
CiVEC (ECAN Interrupt Code) ................................. 214
CLKDIV (Clock Divisor) ............................................ 137
CORCON (Core Control) ...................................... 22, 83
DCICON1 (DCI Control 1) ........................................ 236
DCICON2 (DCI Control 2) ........................................ 237
DCICON3 (DCI Control 3) ........................................ 238
DCISTAT (DCI Status) ............................................. 239
DMACS0 (DMA Controller Status 0) ........................ 126
DMACS1 (DMA Controller Status 1) ........................ 128
DMAxCNT (DMA Channel x Transfer Count) ........... 125
DMAxCON (DMA Channel x Control)....................... 122
DMAxPAD (DMA Channel x
3 Select) ........................................................... 250
Pointer) ............................................................. 223
Selection) ................................................. 225, 226
Extended Identifier) .......................................... 225
Standard Identifier) ........................................... 224
Mask n Extended Identifier).............................. 227
Mask n Standard Identifier) .............................. 227
Identifier) .......................................... 231, 232, 234
Peripheral Address).......................................... 125
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