PIC16F84A-04I/SO Microchip Technology, PIC16F84A-04I/SO Datasheet - Page 492

• Manufacturer Part Number: PIC16F84A-04I/SO
• Description: IC MCU FLASH 1KX14 EE 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F84A-04I/SO

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16F
• No. Of I/o's: 13
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 68Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 68 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILI3-DB16F84A - BOARD DAUGHTER ICEPIC3309-1075 - ADAPTER 18-SOIC TO 18-SOIC309-1011 - ADAPTER 18-SOIC TO 18-DIP309-1010 - ADAPTER 18-SOIC TO 18-DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PICmicro MID-RANGE MCU FAMILY
26.4.2
DS31026A-page 26-8
Note 1: XT, HS or LP oscillator mode assumed.
INSTRUCTION FLOW
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction
fetched
Instruction
executed
CLKOUT
2: T
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
INT pin
OSC1
PC
(4)
continue in-line.
Wake-up Using Interrupts
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4
= 1024T
Inst(PC - 1)
PC
When interrupts are globally disabled (GIE cleared) and any interrupt source has both its inter-
rupt enable bit and interrupt flag set, one of the following events will occur:
• If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will
Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for
flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP
instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as
an NOP.
To ensure that the WDT is clear, a CLRWDT instruction should be executed before a SLEEP instruc-
tion.
Figure 26-2: Wake-up from Sleep Through Interrupt
OSC
complete as an NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO
bit will not be set and PD bit will not be cleared.
immediately wake-up from sleep. The SLEEP instruction will be completely executed before
the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
(drawing not to scale) This delay will not be there for RC osc mode.
Q1 Q2 Q3 Q4
Inst(PC + 1)
SLEEP
PC+1
Q1
Processor in
SLEEP
PC+2
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
PC+2
Interrupt Latency
Dummy cycle
PC + 2
(2)
Q1 Q2 Q3 Q4
Inst(0004h)
Dummy cycle
1997 Microchip Technology Inc.
0004h
Q1 Q2 Q3 Q4
Inst(0005h)
Inst(0004h)
0005h