DSPIC33FJ64GS608-E/PT Microchip Technology, DSPIC33FJ64GS608-E/PT Datasheet - Page 35
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DSPIC33FJ64GS608-E/PT
Manufacturer Part Number
DSPIC33FJ64GS608-E/PT
Description
MCU/DSP 16BIT 64KB FLASH 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ32GS406-IPT.pdf
(418 pages)
Specifications of DSPIC33FJ64GS608-E/PT
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
80-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
Number Of I /o
74
Ram Size
9K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Numeric And Arithmetic Format
Fixed-Point or Floating-Point
Instruction Set Architecture
Harvard
Device Million Instructions Per Second
40 MIPs
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
74
Data Ram Size
4 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 18 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Quantity
Price
Company:
Part Number:
DSPIC33FJ64GS608-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
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Manufacturer:
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3.0
The
dsPIC33FJ64GS406/606/608/610 CPU module has a
16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies from device to
device. A single-cycle instruction prefetch mechanism
is used to help maintain throughput and provides pre-
dictable execution. All instructions execute in a single
cycle, with the exception of instructions that change the
program
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and
interruptible at any point.
The
dsPIC33FJ64GS406/606/608/610 devices have six-
teen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a
data, address or address offset register. The sixteenth
working register (W15) operates as a software Stack
Pointer (SP) for interrupts and calls.
There
dsPIC33FJ32GS406/606/608/610
dsPIC33FJ64GS406/606/608/610 devices: MCU and
DSP. These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the
dsPIC33FJ64GS406/606/608/610 is capable of exe-
cuting a data (or program data) memory read, a work-
ing register (data) read, a data memory write and a
program (instruction) memory read per instruction
2010 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note 1: This data sheet summarizes the features
REPEAT
are
2: Some registers and associated bits
CPU
dsPIC33FJ32GS406/606/608/610
dsPIC33FJ32GS406/606/608/610
dsPIC33FJ32GS406/606/608/610
flow,
of the dsPIC33FJ32GS406/606/608/610
and
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS70204) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip web site
(www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
two
instructions,
the
dsPIC33FJ64GS406/606/608/610
classes
double-word
of
both
instruction
move
of
which
(MOV.D)
in
and
and
and
and
Preliminary
are
the
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1,
and
dsPIC33FJ32GS406/606/608/610
dsPIC33FJ64GS406/606/608/610
Figure 3-2.
3.1
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through
the X memory AGU, which accesses the entire
memory map as one linear data space. Certain DSP
instructions operate through the X and Y AGUs to
support dual operand reads, which splits the data
address space into two parts. The X and Y data space
boundary is device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data space mapping feature lets any
instruction access program space as if it were data
space.
3.2
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits, right or left, in a single cycle. The DSP
instructions
instructions and have been designed for optimal real-
time performance. The MAC instruction and other asso-
ciated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain working
registers to each address space.
the
Data Addressing Overview
DSP Engine Overview
operate
programmer’s
seamlessly
model
DS70591C-page 35
is
with
shown
for
all
other
and
the
in
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