PIC18F67K90-I/PTRSL Microchip Technology, PIC18F67K90-I/PTRSL Datasheet - Page 319
![MCU PIC 128K FLASH XLP 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67K90-I/PTRSL
Manufacturer Part Number
PIC18F67K90-I/PTRSL
Description
MCU PIC 128K FLASH XLP 64TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F67K90-I/PTRSL
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
3828Byte
Cpu Speed
16MIPS
No. Of Timers
11
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
53
Number Of Timers
11
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DM163030, DM180021, DM183026-2, DM183032, DV164131, MA180027
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67K90-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
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21.4.3.5
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPxSTAT
register is cleared. The received address is loaded into
the SSPxBUF register and the SDAx line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit, BF (SSPxSTAT<0>),
is set or bit, SSPOV (SSPxCON1<6>), is set.
An MSSP interrupt is generated for each data transfer
byte. The interrupt flag bit, SSPxIF, must be cleared in
software. The SSPxSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPxCON2<0> = 1), SCLx will be
held low (clock stretch) following each data transfer. The
clock must be released by setting bit, CKP
(SSPxCON1<4>).
Stretching” for more details.
2010 Microchip Technology Inc.
Reception
See
Section 21.4.4
“Clock
Preliminary
PIC18F87K90 FAMILY
21.4.3.6
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register. The ACK pulse will
be sent on the ninth bit and pin, SCLx, is held low
regardless of SEN (see Section 21.4.4 “Clock
Stretching” for more details). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPxBUF regis-
ter which also loads the SSPxSR register. Then, pin,
SCLx, should be enabled by setting bit, CKP
(SSPxCON1<4>). The eight data bits are shifted out on
the falling edge of the SCLx input. This ensures that the
SDAx signal is valid during the SCLx high time
(Figure 21-10).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCLx input pulse. If the
SDAx line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset and the slave monitors for
another occurrence of the Start bit. If the SDAx line was
low (ACK), the next transmit data must be loaded into
the SSPxBUF register. Again, pin, SCLx, must be
enabled by setting bit, CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared in software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.
Transmission
DS39957B-page 319
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