PIC24FJ64GB004-I/PT Microchip Technology, PIC24FJ64GB004-I/PT Datasheet - Page 50
![IC MCU 16BIT 64KB FLASH 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC24FJ64GB004-I/PT
Manufacturer Part Number
PIC24FJ64GB004-I/PT
Description
IC MCU 16BIT 64KB FLASH 44TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24FJ32GA102-ISP.pdf
(48 pages)
2.PIC24FJ32GB002-ISO.pdf
(352 pages)
3.PIC24FJ32GB002-ISO.pdf
(12 pages)
4.PIC24FJ32GB002-ISO.pdf
(342 pages)
Specifications of PIC24FJ64GB004-I/PT
Core Size
16-Bit
Program Memory Size
64KB (22K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC24
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Interface
I2C, LIN, SPI, UART, USB
No. Of Pwm Channels
5
Embedded Interface Type
I2C, LIN, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
33
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
A/d Bit Size
10 bit
A/d Channels Available
13
Height
1 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ64GB004-I/PT
Manufacturer:
NEC
Quantity:
201
Company:
Part Number:
PIC24FJ64GB004-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC24FJ64GB004-I/PT
Manufacturer:
MICROHCIP
Quantity:
20 000
- PIC24FJ32GA102-ISP PDF datasheet
- PIC24FJ32GB002-ISO PDF datasheet #2
- PIC24FJ32GB002-ISO PDF datasheet #3
- PIC24FJ32GB002-ISO PDF datasheet #4
- Current page: 50 of 342
- Download datasheet (6Mb)
program space word as data.
PIC24FJ64GB004 FAMILY
4.3.2
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going through
data space. The TBLRDH and TBLWTH instructions are
the only method to read or write the upper 8 bits of a
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two, 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1.
FIGURE 4-6:
DS39940C-page 48
TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P<15:0>) to a data address (D<15:0>).
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when the byte select is ‘1’; the lower
byte is selected when it is ‘0’.
TBLPAG
02
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
23
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
15
0
000000h
020000h
030000h
800000h
Program Space
Preliminary
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
2.
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table
Memory Page Address register (TBLPAG). TBLPAG
covers the entire program memory space of the
device, including user and configuration spaces. When
TBLPAG<7> = 0, the table page is located in the user
memory space. When TBLPAG<7> = 1, the page is
located in configuration space.
Note:
‘Phantom’ Byte
TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P<23:16>) to a data address. Note that
D<15:8>, the ‘phantom’ byte, will always be ‘0’.
In Byte mode, it maps the upper or lower byte of
the program word to D<7:0> of the data
address, as above. Note that the data will
always be ‘0’ when the upper ‘phantom’ byte is
selected (byte select = 1).
00000000
00000000
00000000
00000000
Only table read operations will execute in
the configuration memory space, and only
then, in implemented areas, such as the
Device ID. Table write operations are not
allowed.
23
© 2009 Microchip Technology Inc.
16
Data EA<15:0>
8
0
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