PIC16C72A-20I/SP Microchip Technology, PIC16C72A-20I/SP Datasheet - Page 26
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PIC16C72A-20I/SP
Manufacturer Part Number
PIC16C72A-20I/SP
Description
IC MCU OTP 2KX14 A/D PWM 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C62B-04SO.pdf
(120 pages)
4.PIC16C72A-04SP.pdf
(6 pages)
Specifications of PIC16C72A-20I/SP
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC16C
No. Of I/o's
22
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
Interface
I2C, SPI
No. Of Pwm Channels
1
Embedded Interface Type
I2C, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16C72A-20I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16C62B/72A
4.2.1
The prescaler assignment is fully under software con-
trol, (i.e., it can be changed “on-the-fly” during program
execution).
FIGURE 4-2:
TABLE 4-1
DS35008B-page 26
Address
01h
0Bh,8Bh
81h
85h
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
Note:
RA4/T0CKI
CLKOUT (= Fosc/4)
WDT Enable bit
Watchdog
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
pin
Timer
SWITCHING PRESCALER ASSIGNMENT
To avoid an unintended device RESET, a
specific instruction sequence (shown in the
PICmicro™ Mid-Range Reference Man-
ual, DS33023) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
Name
TMR0
INTCON
OPTION_REG
TRISA
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
REGISTERS ASSOCIATED WITH TIMER0
T0SE
0
1
Timer0 module’s register
RBPU INTEDG T0CS
Bit 7
GIE
PSA
—
M
U
X
0
1
PEIE
Bit 6
T0CS
—
M
U
X
PORTA Data Direction Register
Bit 5
T0IE
0
8-bit Prescaler
8 - to - 1MUX
Time-out
8
M U X
WDT
Preliminary
T0SE
INTE
Bit 4
1
0
1
PSA
M
U
X
RBIE
Bit 3
PSA
Prescaler
4.3
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
PSA
Bit 2
T0IF
PS2
PS2:PS0
Timer0 Interrupt
SYNC
T
2
CY
INTF
Bit 1
PS1
RBIF
Bit 0
PS0
1999 Microchip Technology Inc.
TMR0 reg
Data Bus
xxxx xxxx
0000 000x
1111 1111
--11 1111
Value on:
POR,
BOR
8
Set flag bit T0IF
on Overflow
other resets
Value on all
uuuu uuuu
0000 000u
1111 1111
--11 1111