PIC18F47J53-I/ML Microchip Technology, PIC18F47J53-I/ML Datasheet - Page 229

• Manufacturer Part Number: PIC18F47J53-I/ML
• Description: IC PIC MCU 128KB FLASH 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F47J53-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: *
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 34
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Embedded Interface Type: I2C, SPI, USART
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180029 - BOARD DEMO PIC18F47J53 FS USB
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 15-5:
15.5.5
When Timer3/5 gate value status is utilized, it is
possible to read the most current level of the gate con-
trol value. The value is stored in the TxGVAL bit
(TxGCON<2>). The TxGVAL bit is valid even when the
Timer3/5 gate is not enabled (TMRxGE bit is cleared).
 2010 Microchip Technology Inc.
TMRxGIF
TMRxGE
TxGSPM
TxDONE
TxGPOL
Timer3/5
TxGGO/
TxGVAL
TxG_IN
TxGTM
TxCKI
TIMER3/5 GATE VALUE STATUS
TIMER3/5 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
Cleared by Software
N
Counting Enabled on
Rising Edge of TxG
Set by Software
Preliminary
N + 1
Falling Edge of TxGVAL
PIC18F47J53 FAMILY
N + 2
15.5.6
When the Timer3/5 gate event interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of TxGVAL
occurs, the TMRxGIF flag bit in the PIRx register will be
set. If the TMRxGIE bit in the PIEx register is set, then
an interrupt will be recognized.
The TMRxGIF flag bit operates even when the
Timer3/5 gate is not enabled (TMRxGE bit is cleared).
Set by Hardware on
N + 3
TIMER3/5 GATE EVENT
INTERRUPT
Cleared by Hardware on
Falling Edge of TxGVAL
N + 4
DS39964B-page 229
Cleared by
Software