PIC24FJ128GA006-I/PT Microchip Technology, PIC24FJ128GA006-I/PT Datasheet - Page 91
![IC PIC MCU FLASH 128K 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC24FJ128GA006-I/PT
Manufacturer Part Number
PIC24FJ128GA006-I/PT
Description
IC PIC MCU FLASH 128K 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ64GA006-IPT.pdf
(240 pages)
3.PIC24FJ64GA006-IPT.pdf
(22 pages)
4.PIC24FJ128GA008-IPT.pdf
(12 pages)
5.PIC24FJ128GA006-IPT.pdf
(231 pages)
6.PIC24FJ128GA010-IPT.pdf
(230 pages)
Specifications of PIC24FJ128GA006-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (43K x 24)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SPI/I2C/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Controller Family/series
PIC24
No. Of I/o's
53
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ128GA006-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC24FJ128GA006-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
6.4
6.4.1
To configure an interrupt source:
1.
2.
3.
4.
6.4.2
The method that is used to declare an ISR and initialize
the IVT with the correct vector address will depend on
the programming language (i.e., ‘C’ or assembler) and
the language development toolsuite that is used to
develop the application. In general, the user must clear
the interrupt flag in the appropriate IFSx register for the
source of interrupt that the ISR handles. Otherwise, the
ISR will be re-entered immediately after exiting the rou-
tine. If the ISR is coded in assembly language, it must
be terminated using a RETFIE instruction to unstack
the saved PC value, SRL value and old CPU priority
level.
© 2009 Microchip Technology Inc.
Note:
Set the NSTDIS Control bit (INTCON1<15>) if
nested interrupts are not desired.
Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx Control register. The priority
level will depend on the specific application and
type of interrupt source. If multiple priority levels
are not desired, the IPCx register control bits for
all
programmed to the same non-zero value.
Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx Status
register.
Enable the interrupt source by setting the inter-
rupt enable control bit associated with the
source in the appropriate IECx Control register.
Interrupt Setup Procedures
enabled
INITIALIZATION
INTERRUPT SERVICE ROUTINE
At a device Reset, the IPC registers are
initialized, such that all user interrupt
sources are assigned to priority level 4.
interrupt
sources
may
PIC24FJ128GA010 FAMILY
be
6.4.3
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
6.4.4
All user interrupts can be disabled using the following
procedure:
1.
2.
To enable user interrupts, the POP instruction may be
used to restore the previous SR value.
Note that only user interrupts with a priority level of 7 or
less can be disabled. Trap sources (level 8-15) cannot
be disabled.
The DISI instruction provides a convenient way to dis-
able interrupts of priority levels 1-6 for a fixed period of
time. Level 7 interrupt sources are not disabled by the
DISI instruction.
Push the current SR value onto the software
stack using the PUSH instruction.
Force the CPU to priority level 7 by inclusive
ORing the value OEh with SRL.
TRAP SERVICE ROUTINE
INTERRUPT DISABLE
DS39747E-page 91