DSPIC33FJ64MC508-E/PT Microchip Technology, DSPIC33FJ64MC508-E/PT Datasheet - Page 87
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DSPIC33FJ64MC508-E/PT
Manufacturer Part Number
DSPIC33FJ64MC508-E/PT
Description
IC DSPIC MCU/DSP 64K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.MA330013.pdf
(370 pages)
2.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
3.PIC24HJ12GP201-ISO.pdf
(84 pages)
4.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
5.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
Specifications of DSPIC33FJ64MC508-E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- MA330013 PDF datasheet
- DSPIC33FJ12GP201-ISO PDF datasheet #2
- PIC24HJ12GP201-ISO PDF datasheet #3
- DSPIC33FJ64MC506-IPT PDF datasheet #4
- DSPIC33FJ64MC506-IPT PDF datasheet #5
- Current page: 87 of 340
- Download datasheet (5Mb)
7.0
The interrupt controller for the dsPIC33FJXXXMCX06/
X08/X10 family of devices reduces the numerous
peripheral interrupt request signals to a single interrupt
request signal to the dsPIC33FJXXXMCX06/X08/X10
CPU. It has the following features:
• Up to eight processor exceptions and software
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
• Fixed interrupt entry and return latencies
7.1
The Interrupt Vector Table (IVT) is shown in Figure 7-1.
The IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
eight nonmaskable trap vectors plus up to 118 sources
of interrupt. In general, each interrupt source has its
own vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this priority is linked to their position in the
vector table. All other things being equal, lower
addresses have a higher natural priority. For example,
the interrupt associated with vector 0 will take priority
over interrupts at any other vector address.
The
devices implement up to 67 unique interrupts and five
nonmaskable traps. These are summarized in
Table 7-1 and Table 7-2.
© 2009 Microchip Technology Inc.
Note:
traps
source
support
dsPIC33FJXXXMCX06/X08/X10
INTERRUPT CONTROLLER
Interrupt Vector Table
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 6.
“Interrupts” (DS70184) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
dsPIC33FJXXXMCX06/X08/X10
family
of
7.1.1
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 7-1. Access to the
AIVT
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a means to
switch between an application and a support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
7.2
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33FJXXXMCX06/X08/X10 device clears its
registers in response to a Reset, which forces the PC
to zero. The digital signal controller then begins pro-
gram execution at location 0x000000. The user pro-
grams a GOTO instruction at the Reset address, which
redirects program execution to the appropriate start-up
routine.
Note:
is
Reset Sequence
provided
ALTERNATE INTERRUPT VECTOR
TABLE
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
by
the
ALTIVT
DS70287C-page 85
control
bit
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