PIC18F4480-E/P Microchip Technology, PIC18F4480-E/P Datasheet - Page 346
![IC PIC MCU FLASH 8KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4480-E/P
Manufacturer Part Number
PIC18F4480-E/P
Description
IC PIC MCU FLASH 8KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4480-IPT.pdf
(490 pages)
4.PIC18F4480-IPT.pdf
(8 pages)
5.PIC18F4480-IPT.pdf
(6 pages)
6.PIC18F4480-IPT.pdf
(6 pages)
Specifications of PIC18F4480-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, MSSP, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18F4480-IPT PDF datasheet #4
- PIC18F4480-IPT PDF datasheet #5
- PIC18F4480-IPT PDF datasheet #6
- Current page: 346 of 490
- Download datasheet (9Mb)
buffers to detect the source of interrupt.
PIC18F2480/2580/4480/4580
24.15.1
To simplify the interrupt handling process in user firm-
ware, the ECAN module encodes a special set of bits. In
Mode 0, these bits are ICODE<3:1> in the CANSTAT
register. In Mode 1 and 2, these bits are EICODE<4:0> in
the CANSTAT register. Interrupts are internally prioritized
such that the higher priority interrupts are assigned lower
values. Once the highest priority interrupt condition has
been cleared, the code for the next highest priority inter-
rupt that is pending (if any) will be reflected by the ICODE
bits (see Table 24-5). Note that only those interrupt
sources that have their associated interrupt enable bit set
will be reflected in the ICODE bits.
In Mode 2, when a receive message interrupt occurs,
the EICODE bits will always consist of ‘10000’. User
firmware may use FIFO Pointer bits to actually access
the next available buffer.
24.15.2
When the transmit interrupt is enabled, an interrupt will
be generated when the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. In Mode 0, there are separate interrupt enable/
disable and flag bits for each of the three dedicated trans-
mit buffers. The TXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU, resetting the TXBnIF bit to a ‘0’. In Mode 1 and 2,
all transmit buffers share one interrupt enable/disable bit
and one flag bit. In Mode 1 and 2, TXBIE in PIE3 and
TXBIF in PIR3 indicate when a transmit buffer has com-
pleted transmission of its message. TXBnIF, TXBnIE and
TXBnIP in PIR3, PIE3 and IPR3, respectively, are not
used in Mode 1 and 2. Individual transmit buffer interrupts
can be enabled or disabled by setting or clearing TXBIE
and B0IE register bits. When a shared interrupt occurs,
user firmware must poll the TXREQ bit of all transmit
24.15.3
When the receive interrupt is enabled, an interrupt will
be generated when a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving
the End-Of-Frame (EOF) field.
In Mode 0, the RXBnIF bit is set to indicate the source
of the interrupt. The interrupt is cleared by the MCU,
resetting the RXBnIF bit to a ‘0’.
In Mode 1 and 2, all receive buffers share RXBIE,
RXBIF and RXBIP in PIE3, PIR3 and IPR3, respec-
tively. Bits, RXBnIE, RXBnIF and RXBnIP, are not
used. Individual receive buffer interrupts can be con-
trolled by the TXBIE and BIE0 registers. In Mode 1,
when a shared receive interrupt occurs, user firmware
must poll the RXFUL bit of each receive buffer to detect
the source of interrupt. In Mode 2, a receive interrupt
indicates that the new message is loaded into FIFO.
FIFO can be read by using FIFO Pointer bits, FP.
DS39637D-page 346
INTERRUPT CODE BITS
TRANSMIT INTERRUPT
RECEIVE INTERRUPT
TABLE 24-5:
24.15.4
When an error occurs during transmission or reception
of a message, the message error flag, IRXIF, will be set
and if the IRXIE bit is set, an interrupt will be generated.
This is intended to be used to facilitate baud rate
determination when used in conjunction with Listen
Only mode.
24.15.5
When the PIC18F2480/2580/4480/4580 devices are in
Sleep mode and the bus activity wake-up interrupt is
enabled, an interrupt will be generated and the WAKIF
bit will be set when activity is detected on the CAN bus.
This interrupt causes the PIC18F2480/2580/4480/
4580 devices to exit Sleep mode. The interrupt is reset
by the MCU, clearing the WAKIF bit.
24.15.6
When the CAN module error interrupt (ERRIE in PIE3)
is enabled, an interrupt is generated if an overflow con-
dition occurs, or if the error state of the transmitter or
receiver has changed. The error flags in COMSTAT will
indicate one of the following conditions.
Legend:
ERR = ERRIF * ERRIE
TX0 = TXB0IF * TXB0IE RX1 = RXB1IF * RXB1IE
TX1 = TXB1IF * TXB1IE WAK = WAKIF * WAKIE
TX2 = TXB2IF * TXB2IE
ICODE
<2:0>
000
001
010
011
100
101
110
111
Interrupt
Wake on
Interrupt
RXB1
RXB0
TXB2
TXB1
TXB0
None
Error
MESSAGE ERROR INTERRUPT
BUS ACTIVITY WAKE-UP
INTERRUPT
ERROR INTERRUPT
VALUES FOR ICODE<2:0>
ERR•WAK•TX0•TX1•TX2•RX0•RX1
ERR
ERR•TX0•TX1•TX2
ERR•TX0•TX1
ERR•TX0
ERR•TX0•TX1•TX2•RX0•RX1
ERR•TX0•TX1•TX2•RX0
ERR•TX0•TX1•TX2•RX0•RX1•WAK
© 2009 Microchip Technology Inc.
Boolean Expression
RX0 = RXB0IF * RXB0IE
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