PIC24FJ64GB110-I/PF Microchip Technology, PIC24FJ64GB110-I/PF Datasheet - Page 5
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PIC24FJ64GB110-I/PF
Manufacturer Part Number
PIC24FJ64GB110-I/PF
Description
IC PIC MCU FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA106-IPT.pdf
(52 pages)
2.PIC24FJ64GB106-IPT.pdf
(16 pages)
3.PIC24FJ64GB106-IPT.pdf
(352 pages)
4.PIC24FJ192GB108-IPT.pdf
(328 pages)
Specifications of PIC24FJ64GB110-I/PF
Core Size
16-Bit
Program Memory Size
64KB (22K x 24)
Oscillator Type
Internal
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
83
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Controller Family/series
PIC24
No. Of I/o's
83
Ram Memory Size
16384Byte
Cpu Speed
32MHz
No. Of Timers
5
No.
RoHS Compliant
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
84
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ64GB110-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
11. Module: USB
2010 Microchip Technology Inc.
The Bus Activity Interrupt Flag, ACTVIF, is active
only while the device is in Sleep mode. It will not
become set when the microcontroller is in a Run
mode.
Work around
The type of work around depends on the type of
application that the microcontroller is being used
for.
For Self-Powered Peripherals: After receiving a
Suspend command from the PC, do NOT suspend
or disable the USB module. In addition, do not
switch to a clock configuration that is incompatible
with USB operation (refer to the device data sheet
for USB compatible clock settings).
For Bus Powered Peripherals: After receiving a
suspend command from the PC (IDLEIF Interrupt
Flag = 1):
• Suspend the USB module (U1PWRC<1> = 1)
• Globally enable USB interrupts (IEC5<6> = 1)
• Specifically enable the bus activity interrupt
• Place the microcontroller into Sleep mode as
For Embedded Host Devices:
• Issue a suspend command to the peripheral
• Suspend the USB module (U1PWRC<1> = 1)
• Globally enable USB interrupts (IEC5<6> = 1)
• Place the microcontroller into Sleep mode as
As an alternate procedure, do NOT suspend or
disable the USB module and do not switch to a
clock configuration that is incompatible with USB
operation.
Affected Silicon Revisions
A3
(U1OTGIE<4> = 1)
soon as possible
device
soon as possible
X
A5
X
PIC24FJ256GB110 FAMILY
12. Module: UART (UERIF Interrupt)
13. Module: UART (FIFO Error Flags)
14. Module: UART (IrDA
The UART error interrupt may not occur, or occur
at an incorrect time, if multiple errors occur during
a short period of time.
Work around
Read the error flags in the UxSTA register when-
ever a byte is received to verify the error status. In
most cases, these bits will be correct, even if the
UART error interrupt fails to occur. For possible
exceptions, refer to Errata #
Affected Silicon Revisions
Under certain circumstances, the PERR and
FERR error bits may not be correct for all bytes in
the receive FIFO. This has only been observed
when both of the following conditions are met:
• The UART receive interrupt is set to occur
• More than 2 bytes with an error are received
In these cases, only the first two bytes with a parity
or framing error will have the corresponding bits
indicate correctly. The error bits will not be set after
this.
Work around
None.
Affected Silicon Revisions
When the UART is operating in 8-bit mode
(PDSEL<1:0> = 0x) and using the IrDA endec
(IREN = 1), the module incorrectly transmits a
data payload of 80h as 00h.
Work around
None.
Affected Silicon Revisions
A3
A3
A3
when the FIFO is full or ¾ full
(UxSTA<7:6> = 1x)
X
X
X
A5
A5
A5
®
)
13.
DS80369K-page 5