PIC18F4525-E/ML Microchip Technology, PIC18F4525-E/ML Datasheet - Page 120
PIC18F4525-E/ML
Manufacturer Part Number
PIC18F4525-E/ML
Description
IC MCU FLASH 24KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2525-ISO.pdf
(412 pages)
3.PIC18F2525-ISO.pdf
(18 pages)
4.PIC18F2525-ISO.pdf
(18 pages)
5.PIC18F2525-ISO.pdf
(6 pages)
6.PIC18F2525-ISO.pdf
(6 pages)
Specifications of PIC18F4525-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3986 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
1 x 8
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, 53275-917, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13 bit
For Use With
I3DB18F4620 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC18F2221-ISO PDF datasheet
- PIC18F2525-ISO PDF datasheet #2
- PIC18F2525-ISO PDF datasheet #3
- PIC18F2525-ISO PDF datasheet #4
- PIC18F2525-ISO PDF datasheet #5
- PIC18F2525-ISO PDF datasheet #6
- Current page: 120 of 412
- Download datasheet (7Mb)
PIC18F2525/2620/4525/4620
10.4
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Interrupt
Priority registers (IPR1 and IPR2). Using the priority bits
requires that the Interrupt Priority Enable (IPEN) bit be
set.
REGISTER 10-8:
DS39626E-page 118
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
PSPIP
R/W-1
IPR Registers
(1)
This bit is unimplemented on 28-pin devices and will read as ‘0’.
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit
1 = High priority
0 = Low priority
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
RCIP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
TXIP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
R/W-1
ADIP
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
W = Writable bit
‘1’ = Bit is set
R/W-1
RCIP
R/W-1
TXIP
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPIP
R/W-1
(1)
CCP1IP
R/W-1
© 2008 Microchip Technology Inc.
x = Bit is unknown
TMR2IP
R/W-1
TMR1IP
R/W-1
bit 0
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