PIC18F4410-I/PT Microchip Technology, PIC18F4410-I/PT Datasheet - Page 253

• Manufacturer Part Number: PIC18F4410-I/PT
• Description: IC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4410-I/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 36
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

22.5.1
The program memory may be read to or written from
any location using the table read and table write
instructions. The Device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In Normal Execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. The
EBTRn bits control table reads. For a block of user
memory with the EBTRn bit set to ‘0’, a table read
instruction that executes from within that block is
allowed to read. A table read instruction that executes
FIGURE 22-7:
© 2009 Microchip Technology Inc.
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TBLPTR = 0008FFh
PROGRAM MEMORY
CODE PROTECTION
Register Values
PC = 003FFEh
TABLAT register returns a value of ‘0’.
EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
(16-KBYTE AND 32-KBYTE DEVICES)
Program Memory
TBLRD*
from a location outside of that block is not allowed to
read and will result in reading ‘0’s. Figures 22-7
through 22-10 illustrate table write and table read
protection.
Note:
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
PIC18F2X1X/4X1X
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
Configuration Bit Settings
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
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