PIC16LC926-I/PT Microchip Technology, PIC16LC926-I/PT Datasheet - Page 57

• Manufacturer Part Number: PIC16LC926-I/PT
• Description: IC MCU CMOS 20MHZ 8K W/LCD64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC926-I/PT

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: OTP
• Ram Size: 336 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC16C
• No. Of I/o's: 25
• Ram Memory Size: 336Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Interface: I2C, SPI
• Embedded Interface Type: I2C, SPI
• Rohs Compliant: Yes
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 336 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, a compare interrupt is also generated.
FIGURE 8-2:
8.2.1
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
RC2/CCP1
Note:
2001 Microchip Technology Inc.
Output Enable
TRISC<2>
Special event trigger will reset Timer1, but not
set interrupt flag bit TMR1IF (PIR1<0>).
Compare Mode
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.
CCP PIN CONFIGURATION
Q
R
CCP1CON<3:0>
S
Mode Select
Output
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
Set CCP1IF
PIR1<2>
Match
CCPR1H CCPR1L
TMR1H
Comparator
TMR1L
Preliminary
8.2.2
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3
When Generate Software Interrupt is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is gen-
erated (if enabled).
8.2.4
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion. This
allows the CCPR1H:CCPR1L register pair to effectively
be a 16-bit programmable period register for Timer1.
Note:
The “special event trigger” from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
PIC16C925/926
DS39544A-page 55