AT90USB646-MUR Atmel, AT90USB646-MUR Datasheet - Page 295

• Manufacturer Part Number: AT90USB646-MUR
• Description: MCU AVR 64K FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB646-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.14 IN Pipe management
7593K–AVR–11/09
If the OUT Pipe is composed of multiple banks, this also switches to the next data bank. The
TXOUT and FIFOCON bits are automatically updated by hardware regarding the status of the
next bank.
The Pipe must be configured first.
When the Host requires data from the device, the firmware has to determine first the IN mode to
use using the INMODE bit:
The IN request generation will start when the firmware clear the PFREEZE bit.
• INMODE = 0. The INRQX register is taken in account. The Host controller will perform
• INMODE = 1. The USB controller will perform infinite IN request until the firmware freezes the
(INRQX+1) IN requests on the selected Pipe before freezing the Pipe. This mode avoids to
have extra IN requests on a Pipe.
Pipe.
Example with 1 OUT data bank
Example with 2 OUT data banks
Example with 2 OUT data banks
FIFOCON
FIFOCON
FIFOCON
TXOUT
TXOUT
TXOUT
SW
SW
SW
write data from CPU
write data from CPU
write data from CPU
BANK 0
BANK 0
BANK 0
SW
SW
SW
OUT
OUT
OUT
SW
SW
write data from CPU
write data from CPU
(bank 0)
DATA
BANK 1
BANK 1
(bank 0)
(bank 0)
DATA
DATA
ACK
HW
SW
HW
HW
ACK
ACK
SW
OUT
SW
SW
SW
OUT
write data from CPU
write data from CPU
write data from CPU
(bank 1)
DATA
AT90USB64/128
BANK 0
BANK0
BANK0
ACK
(bank 1)
DATA
SW
OUT
ACK
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