PIC18F4525-E/P Microchip Technology, PIC18F4525-E/P Datasheet - Page 6
![IC MCU FLASH 24KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4525-E/P
Manufacturer Part Number
PIC18F4525-E/P
Description
IC MCU FLASH 24KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2525-ISO.pdf
(412 pages)
3.PIC18F2525-ISO.pdf
(18 pages)
4.PIC18F2525-ISO.pdf
(18 pages)
5.PIC18F2525-ISO.pdf
(6 pages)
6.PIC18F2525-ISO.pdf
(6 pages)
7.PIC18LF4620-IP.pdf
(390 pages)
Specifications of PIC18F4525-E/P
Program Memory Type
FLASH
Program Memory Size
48KB (24K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3986 B
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, 53275-917, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DB18F4620 - BOARD DAUGHTER ICEPIC3DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4525-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F2525/2620/4525/4620
18. Module: EUSART
19. Module: Timer1/Timer3
20. Module: Timer1/Timer3
DS80200D-page 6
When performing back-to-back transmission in 9-bit
mode (TX9D bit in the TXSTA register is set), the
second byte may be corrupted if it is written into
TXREG immediately after the TMRT bit is set.
Work around
Execute a software delay, at least one half the
transmission’s bit time, after TMRT is set and prior
to writing subsequent bytes into TXREG.
Date Codes that pertain to this issue:
All engineering and production devices.
When Timer1 or Timer3 is configured for the
external clock source and the CCPxCON register
is configured with 0x0B (Compare mode, trigger
special event), the timer is not reset on a Special
Event Trigger.
Work around
Modify firmware to reset the Timer registers upon
detection of the compare match condition —
TMRxL and TMRxH.
Date Codes that pertain to this issue:
All engineering and production devices.
When Timer1 or Timer3 is in External Clock
Synchronized mode and the external clock period
is between 1 and 2 T
be skipped.
Work around
Avoid using an external clock with a period (1/
frequency) between 1 and 2 T
Date Codes that pertain to this issue:
All engineering and production devices.
CY
, interrupts will occasionally
CY
.
21. Module: Timer1/Timer3
22. Module: MSSP
When Timer1/Timer3 is operating in 16-bit mode
and the prescale setting is not 1:1, a write to the
TMR1H/TMR3H Buffer registers may lengthen the
duration of the period between the increments of
the timer for the period in which TMR1H/TMR3H
were written.
Work around
Two work arounds are available: 1) Stop Timer1/
Timer3 before writing the TMR1H/TMR3H regis-
ters; 2) Write TMR1L/TMR3L immediately after
writing TMR1H/TMR3H.
Date Codes that pertain to this issue:
All engineering and production devices.
I
bit should be set) only when the system is idle
(i.e., when ACKEN, RCEN, PEN, RSEN and SEN
all equal zero). It should not be possible to set the
RCEN bit when the system is not idle, however,
the RCEN bit can be set under this circumstance.
Work around
Wait for the system to become idle before setting the
RCEN bit. This requires a check for the following bits
to be clear:
ACKEN, RCEN, PEN, RSEN and SEN.
Date Codes that pertain to this issue:
All engineering and production devices.
2
C Receive mode should be enabled (i.e., RCEN
© 2006 Microchip Technology Inc.