PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 5
![IC PIC MCU 128KB FLASH 28QFN](/photos/18/33/183309/qfn-28_sml.jpg)
PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
The Configuration Words for these devices are located
at addresses, 300000h through 300007h. These are
implemented as three pairs of volatile memory regis-
ters. Each register is automatically loaded from a copy
stored at the end of program memory. For this reason,
the last four words (or eight bytes) of the code space
(also called the Flash Configuration Words) should be
written with configuration data and not executable
code. The addresses of the Flash Configuration Words
are also listed in Table 2-2. Refer to section Section 5.0
“Configuration Word” for more information.
Locations, 3FFFFEh and 3FFFFFh, are reserved for
the device ID bits. These bits may be used by the
programmer to identify what device type is being pro-
grammed and are described in Section 5.1 “Device ID
Word”. These device ID bits read out normally, even
after code protection.
© 2009 Microchip Technology Inc.
PIC18F2XJXX/4XJXX FAMILY
2.2.1
Memory in the device address space (000000h to
3FFFFFh) is addressed via the Table Pointer register,
which in turn, is comprised of three registers:
• TBLPTRU at RAM address 0FF8h
• TBLPTRH at RAM address 0FF7h
• TBLPTRL at RAM address 0FF6h
The 4-bit command, ‘0000’ (core instruction), is used to
load the Table Pointer prior to using many read or write
operations.
Addr[21:16]
TBLPTRU
MEMORY ADDRESS POINTER
TBLPTRH
Addr[15:8]
DS39687E-page 5
TBLPTRL
Addr[7:0]