PIC18LF27J53-I/ML Microchip Technology, PIC18LF27J53-I/ML Datasheet - Page 3

• Manufacturer Part Number: PIC18LF27J53-I/ML
• Description: IC PIC MCU 128KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J53-I/ML

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To 3.6V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: Charge Time Measurement Unit
2. Module: Phase Locked Loop (PLL)
 2010 Microchip Technology Inc.
Note:
When using the CTMU, the constant current
source may not output if the internal band gap
reference is not enabled.
Work around
Before using the CTMU, the internal band gap ref-
erence module should be manually enabled by
setting the VBGEN bit to ‘1’ (ANCON1<7> = 1).
Affected Silicon Revisions
When OSCCON<6:4> are configured to settings
other than a 4 MHz or 8 MHz INTOSC post-
scaler, the PLLEN bit (OSCTUNE<6>) is forced
to ‘0’, even if firmware tries to set the PLLEN bit.
This may prevent firmware from enabling the
PLL.
Work around
Before attempting to set the PLLEN bit, config-
ure OSCCON<6:4> to ‘0b110’ or ‘0b111’ to
select the 4 MHz or 8 MHz INTOSC postscaler.
Affected Silicon Revisions
A1
A1
X
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A1).
(CTMU)
PIC18F47J53 FAMILY
3. Module: Analog-to-Digital Converter
At the beginning of sample acquisition, one or
more small pull-up pulses (approximately 25 ns
long) may output to the currently selected ANx
analog channel. These pulses can lead to a pos-
itive offset error when the analog signal voltage
is near V
is unable to dissipate the added pull-up voltage
before the A/D conversion occurs.
Work around
Do one or more of the following:
• Use the “0 T
• Use a longer A/D acquisition time setting to
• Use low-impedance, active analog signal
• Experiment with external filter capacitor val-
Small filter capacitor values (or none at all) will
allow time for the external analog signal driver to
dissipate the pull-up voltage quickly. Alternately,
large filter capacitor values will prevent the short
pull-up pulses from increasing the final voltage
enough to cause an A/D conversion error.
Affected Silicon Revisions
A1
start the next sample acquisition period imme-
diately following an A/D conversion
completion.
This allows the external analog signal driver
more time to dissipate the pull-up pulses that
occur when the sample acquisition is started.
provide time for the external analog signal
driver to dissipate the pull-up pulse voltage.
drivers to reduce the time needed to dissipate
the pull-up pulse voltage.
ues to avoid allowing the pull-up voltage offset
to affect the final voltage that gets converted.
X
SS
(ADC)
and the external analog signal driver
AD
” A/D acquisition time setting to
DS80506C-page 3