PIC18LF27J53-I/ML Microchip Technology, PIC18LF27J53-I/ML Datasheet - Page 154
PIC18LF27J53-I/ML
Manufacturer Part Number
PIC18LF27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18LF27J53-I/ML
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 3.6V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF27J53-I/ML
Manufacturer:
ATMEL
Quantity:
101
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 154 of 496
- Download datasheet (5Mb)
PIC18(L)F2X/4XK22
REGISTER 10-7:
REGISTER 10-8:
REGISTER 10-9:
DS41412D-page 154
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-3
bit 2-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-3
bit 2-0
Note 1:
WPUE3
TRISx7
R/W-1
R/W-1
U-0
—
Available on PIC18(L)F4XK22 devices only.
Register description for TRISA, TRISB, TRISC and TRISD.
Available on PIC18(L)F4XK22 devices only.
Unimplemented: Read as ‘0’
ANSE<2:0>: RE<2:0> Analog Select bit
1 = Digital input buffer disabled
0 = Digital input buffer enabled
TRISx<7:0>: PORTx Tri-State Control bit
1 = PORTx pin configured as an input (tri-stated)
0 = PORTx pin configured as an output
WPUE3: Weak Pull-up Register bits
1 = Pull-up enabled on PORT pin
0 = Pull-up disabled on PORT pin
Unimplemented: Read as ‘0’
TRISE<7:0>: PORTE Tri-State Control bit
1 = PORTE pin configured as an input (tri-stated)
0 = PORTE pin configured as an output
TRISx6
R/W-1
U-0
U-0
—
—
ANSELE – PORTE ANALOG SELECT REGISTER
TRISx: PORTx TRI-STATE REGISTER
TRISE: PORTE TRI-STATE REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
TRISx5
R/W-1
U-0
U-0
—
—
TRISx4
R/W-1
U-0
U-0
Preliminary
—
—
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRISx3
R/W-1
U-0
U-0
—
—
(1)
TRISE2
ANSE2
TRISx2
R/W-1
R/W-1
R/W-1
(1)
(1)
2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
x = Bit is unknown
TRISE1
ANSE1
TRISx1
R/W-1
R/W-1
R/W-1
(1)
(1)
TRISE0
ANSE0
TRISx0
R/W-1
R/W-1
R/W-1
bit 0
bit 0
bit 0
(1)
(1)
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