PIC24FJ192GA108T-I/PT Microchip Technology, PIC24FJ192GA108T-I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC24FJ192GA108T-I/PT
• Description: IC PIC MCU FLASH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ192GA108T-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 192KB (65.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: MA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC24FJ192GA108T-I/PTTR

PIC24FJ256GA110 FAMILY
TABLE 2:
DS80368J-page 2
Core
Core
JTAG
UART
I/O
SPI
CTMU
UART
UART
SPI
UART
UART
UART
Core
Memory
ICSP™
RTCC
I
Module
I
Module
A/D Converter
SPI
Core
SPI/PPS
Oscillator
CTMU
Output 
Compare
Interrupts
A/D Converter
Note 1:
2
2
C™
C™
Module
Only those issues indicated in the last column apply to the current silicon revision.
SILICON ISSUE SUMMARY
RAM Operation
BOR
Device 
Programming
PORTB
Master mode
UERIF Interrupt
FIFO Error Flags
Enhanced Buffer
modes
IrDA
IrDA
IrDA
Instruction Set
Program Space 
Visibility
Master mode
Slave mode
Enhanced Buffer
mode
Code Protection
LPRC
A/D Trigger
INTx
Feature
®
—
—
—
—
—
—
—
—
Number
Item
10.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
11.
1.
3.
4.
5.
6.
7.
2.
8.
9.
RAM issues in Doze mode.
BOR issues in enabled on-chip regulator.
JTAG issues in device programming.
Framing errors in UART.
RB5 issues in open-drain operation.
Early one-half clock cycles.
CTMU issues as a trigger source.
UART error interrupt issue.
Error bits settings for receive FIFO.
Errors in enhanced buffer interrupts.
Issues in 8-bit mode using IrDA
Framing errors in 8-bit mode using IrDA
endec.
Transmission errors in 9-bit mode using IrDA
endec.
Read-After-Write stall conditions inside a
REPEAT loop.
False error trap conditions when accessing
data in the PSV.
Inability of the ICSP/ICD port pair to read or
program.
Unexpected decrementing of the Alarm
Repeat Counter.
Acknowledgement issues in addressing slave
device.
Acknowledgement issues in Slave mode.
Debugging issues on 64-pin devices.
FIFO transfer issues in Enhanced Master
mode.
Applications unable to write when General
Segment Code Protection has been enabled.
ALTRP/ASCK1 functionality is not supported.
Issues with LPRC automatic restart following
BOR.
Issues in the CTMU in triggering automatic
A/D conversion.
Single missed compare events under certain
conditions.
External interrupts missed when writing to
INTCON2.
Module continues to draw current when
disabled.
Issue Summary
®
endec.
 2010 Microchip Technology Inc.
A3
Revisions
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
A5
(1)
X
X
X
X
X