PIC24FJ128GA110-E/PT Microchip Technology, PIC24FJ128GA110-E/PT Datasheet - Page 304

• Manufacturer Part Number: PIC24FJ128GA110-E/PT
• Description: IC PIC MCU FLASH 128KB 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA110-E/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (43K x 24)
• Package / Case: 100-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ256GA110 FAMILY
D
Data Memory
DC Characteristics
Development Support ....................................................... 255
Device Features (Summary)
Doze Mode........................................................................ 124
E
Electrical Characteristics................................................... 267
ENVREG Pin..................................................................... 249
Equations
Errata .................................................................................... 8
F
Flash Configuration Words.................................................. 34
Flash Program Memory
I
I/O Ports ............................................................................ 125
DS39905D-page 304
Address Space............................................................ 35
Memory Map ............................................................... 35
Near Data Space ........................................................ 36
SFR Space.................................................................. 36
Software Stack ............................................................ 51
Space Organization .................................................... 36
I/O Pin Input Specifications ....................................... 275
I/O Pin Output Specifications .................................... 276
Idle Current ............................................................... 271
Internal Voltage Regulator Specifications ................. 277
Operating Current ..................................................... 270
Power-Down Current ................................................ 273
Program Memory ...................................................... 276
Temperature and Voltage Specifications .................. 269
100-Pin........................................................................ 13
64-Pin.......................................................................... 11
80-Pin.......................................................................... 12
Absolute Maximum Ratings ...................................... 267
Thermal Operating Conditions .................................. 268
V/F Graph ................................................................. 268
A/D Conversion Clock Period ................................... 231
Calculating the PWM Period ..................................... 168
Calculation for Maximum PWM Resolution............... 169
Computing Baud Rate Reload Value ........................ 185
Relationship Between Device and SPI
RTCC Calibration ...................................................... 217
UART Baud Rate with BRGH = 0 ............................. 192
UART Baud Rate with BRGH = 1 ............................. 192
and Table Instructions................................................. 55
Enhanced ICSP Operation.......................................... 56
JTAG Operation .......................................................... 56
Operations .................................................................. 56
Programming Algorithm .............................................. 58
RTSP Operation.......................................................... 56
Single-Word Programming.......................................... 61
Analog Port Configuration ......................................... 126
Input Change Notification.......................................... 127
Open-Drain Configuration ......................................... 126
Peripheral Pin Select ................................................ 127
Pull-ups and Pull-Downs ........................................... 127
Clock Speed...................................................... 182
I
Input Capture
Input Capture with Dedicated Timer ................................. 161
Instruction Set
Instruction-Based Power-Saving Modes
Inter-Integrated Circuit (I
Inter-Integrated Circuit. See I
Internet Address ............................................................... 305
Interrupt Controller.............................................................. 69
Interrupt Vector Table (IVT) ................................................ 69
Interrupts
J
JTAG Interface.................................................................. 253
M
Microchip Internet Web Site.............................................. 305
MPLAB ASM30 Assembler, Linker, Librarian ................... 256
MPLAB Integrated Development
MPLAB PM3 Device Programmer .................................... 258
MPLAB REAL ICE In-Circuit Emulator System ................ 257
MPLINK Object Linker/MPLIB Object Librarian ................ 256
N
Near Data Space ................................................................ 36
O
Oscillator Configuration
Output Compare
Output Compare with Dedicated Timer ............................ 165
P
Packaging ......................................................................... 285
Parallel Master Port. See PMP. ........................................ 199
Peripheral Enable Bits ...................................................... 124
Peripheral Module Disable Bits......................................... 124
2
C
Clock Rates .............................................................. 185
Communicating as Master in Single
Peripheral Remapping Options................................. 183
Reserved Addresses ................................................ 185
Setting Baud Rate When Operating as
Slave Address Masking ............................................ 185
32-Bit Cascaded Mode ............................................. 162
Operations ................................................................ 162
Synchronous and Trigger Modes.............................. 161
Overview................................................................... 261
Summary .................................................................. 259
Idle Mode .......................................................... 123, 124
and Reset Sequence .................................................. 69
Implemented Vectors.................................................. 71
Setup and Service Procedures ................................. 111
Trap Vectors ............................................................... 70
Vector Table ............................................................... 70
Environment Software .............................................. 255
Bit Values for Clock Selection................................... 114
Clock Switching ........................................................ 118
CPU Clocking Scheme ............................................. 114
Initial Configuration on POR ..................................... 114
Cascaded (32-Bit) Mode........................................... 165
Operations ................................................................ 166
Synchronous and Trigger Modes.............................. 165
Details....................................................................... 287
Marking ..................................................................... 285
Master Environment ......................................... 183
Bus Master ....................................................... 185
Sequence ......................................................... 119
2
C) ............................................. 183
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2
C. ...................................... 183