PIC16C62A-10/SP Microchip Technology, PIC16C62A-10/SP Datasheet - Page 213
![IC MCU OTP 2KX14 PWM 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16C62A-10/SP
Manufacturer Part Number
PIC16C62A-10/SP
Description
IC MCU OTP 2KX14 PWM 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16LC62A-04SP.pdf
(337 pages)
4.PIC16C62A-04SP.pdf
(8 pages)
Specifications of PIC16C62A-10/SP
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16LC62A-04SP PDF datasheet #3
- PIC16C62A-04SP PDF datasheet #4
- Current page: 213 of 337
- Download datasheet (3Mb)
FIGURE 19-11: I
TABLE 19-10: I
Parameter
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
1997 Microchip Technology Inc.
100*
101*
102*
103*
106*
107*
109*
110*
No.
90*
91*
92*
*
2: A fast-mode (400 kHz) I
These parameters are characterized but not tested.
Note: Refer to Figure 19-1 for load conditions
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
tsu;DAT
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
T
released.
SDA
Out
SDA
In
SCL
R
max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I
T
T
T
T
T
T
T
HD
HD
SU
SU
SU
T
Sym
T
HIGH
LOW
T
Cb
T
BUF
AA
:
:
:
:
:
R
F
STO
STA
STA
DAT
DAT
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
2
2
C BUS DATA TIMING
C BUS DATA REQUIREMENTS
Characteristic
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall time 100 kHz mode
START condition
setup time
START condition hold
time
Data input hold time
Data input setup time
STOP condition setup
time
Output valid from
clock
Bus free time
Bus capacitive loading
90
103
91
2
C-bus device can be used in a standard-mode (100 kHz) I
109
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100
106
101
109
20 + 0.1Cb
20 + 0.1Cb
1.5T
1.5T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
107
CY
CY
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C bus specification) before the SCL line is
2
Units
C-bus system, but the requirement
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
92
Device must operate at a min-
imum of 1.5 MHz
Device must operate at a min-
imum of 10 MHz
Device must operate at a min-
imum of 1.5 MHz
Device must operate at a min-
imum of 10 MHz
Cb is specified to be from
10-400 pF
Cb is specified to be from
10-400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can
start
PIC16C6X
102
110
DS30234D-page 213
Conditions
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