PIC18F66J50-I/PT Microchip Technology, PIC18F66J50-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F66J50-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J50-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 49
• Ram Memory Size: 3.8125KB
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Silicon Errata Issues
1. Module: MSSP (I
EXAMPLE 1:
© 2009 Microchip Technology Inc.
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf
nop
nop
;CPU may now execute 2 cycle instructions
Note:
When configured for I
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPBUF) is not
read after the SSPIF interrupt (PIR1<3>) has
occurred, but before the first rising clock edge of
the next byte being received.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPIF is set, read the SSPBUF
Affected Silicon Revisions
Affected Silicon Revisions
A2
A2
clock stretching feature.
This
(SSPCON2<0>).
before the first rising clock edge of the next byte
being received.
X
X
RCSTA1, SPEN ;or RCSTA2 if EUSART2
;1 Tcy delay
;1 Tcy delay (two total)
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A4).
A3
A3
X
X
is
done
A4
A4
2
X
X
RE-ENABLING A EUSART MODULE
C slave reception, enable the
2
by
C™ Slave)
2
C™ slave reception, the
setting
the
SEN
bit
PIC18F87J50 FAMILY
2. Module: MSSP (I
3. Module: Enhanced Universal
When in I
clock stretching, the first clock pulse after the slave
releases the SCL line may be narrower than the
configured clock width. This may result in the slave
missing the first clock in the next transmission/
reception.
Work around
The clock pulse will be the normal width if the slave
does not perform clock stretching.
Affected Silicon Revisions
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled
• The EUSART is re-enabled (RCSTAx<7> = 1)
• A two-cycle instruction is executed immediately
Work around
Add a 2 T
enables the EUSART module (ex: sets SPEN = 1).
See Example 1.
A2
(SPEN bit (RCSTAx<7>) = 0)
after enabling the module (setting SPEN,
CREN or TXEN = 1)
X
A3
X
2
Synchronous Asynchronous
Receiver Transmitter (EUSART)
CY
C Master mode, if the slave performs
A4
delay after any instruction that re-
X
2
C™ Master)
DS80481A-page 3