PIC18F4431-E/PT Microchip Technology, PIC18F4431-E/PT Datasheet - Page 10

• Manufacturer Part Number: PIC18F4431-E/PT
• Description: IC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
3.1.1
When using low voltage ICSP, the part must be sup-
plied by the voltage specified in parameter #D111 if a
bulk erase is to be executed. All other bulk erase details
as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the bulk erase
limit, refer to the erase methodology described in
Sections 3.1.2 and 3.2.2.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the bulk erase
limit, follow the methodology described in Section 3.3
and write ones to the array.
3.1.2
Irrespective of whether high or low voltage ICSP is
used, it is possible to erase single row (64 bytes of
data) in all panels at once. For example, in the case of
a 16-Kbyte device (4 panels), 512 bytes through 64
bytes in each panel can be erased simultaneously dur-
ing each erase sequence. In this case, the offset of the
erase within each panel is the same (see Figure 3-5).
Multi-panel single row erase is enabled by appropri-
ately configuring the Programming Control register
located at 3C0006h.
DS30500B-page 10
LOW VOLTAGE ICSP BULK ERASE
ICSP MULTI-PANEL SINGLE ROW
ERASE
The multi-panel single row erase duration is externally
timed and is controlled by SCLK. After a “Start Pro-
gramming” command is issued (4-bit, ‘1111’), a NOP is
issued, where the 4th SCLK is held high for the
duration of the programming time, P9.
After SCLK is brought low, the programming sequence
is terminated. SCLK must be held low for the time spec-
ified by parameter P10 to allow high voltage discharge
of the memory array.
The code sequence to program a PIC18FXX31 device
is shown in Table 3-3. The flowchart shown in
Figure 3-3 depicts the logic necessary to completely
erase a PIC18FXX31 device. The timing diagram that
details the “Start Programming” command, and
parameters P9 and P10 is shown in Figure 3-6.
Note:
The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.
 2010 Microchip Technology Inc.