DSPIC33FJ12MC202-I/SP Microchip Technology, DSPIC33FJ12MC202-I/SP Datasheet - Page 162
![IC DSPIC MCU/DSP 12K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ12MC202-I/SP
Manufacturer Part Number
DSPIC33FJ12MC202-I/SP
Description
IC DSPIC MCU/DSP 12K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
4.DSPIC33FJ12MC202-IML.pdf
(282 pages)
Specifications of DSPIC33FJ12MC202-I/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164337 - MODULE SOCKET FOR PM3 40DIPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC24HJ12GP201-ISO PDF datasheet
- DSPIC33FJ12MC201-ISO PDF datasheet #2
- DSPIC33FJ12MC201-ISO PDF datasheet #3
- DSPIC33FJ12MC202-IML PDF datasheet #4
- Current page: 162 of 282
- Download datasheet (4Mb)
dsPIC33FJ12MC201/202
REGISTER 15-1:
DS70265C-page 160
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-8
bit 7
bit 6
bit 5
CNTERR
SWPAB
R/W-0
R/W-0
CNTERR: Count Error Status Flag bit
1 = Position count error has occurred
0 = No position count error has occurred
Unimplemented: Read as ‘0’
QEISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
INDEX: Index Pin State Status bit (Read-Only)
1 = Index pin is High
0 = Index pin is Low
UPDN: Position Counter Direction Status bit
1 = Position Counter Direction is positive (+)
0 = Position Counter Direction is negative (-)
QEIM<2:0>: Quadrature Encoder Interface Mode Select bits
111 = Quadrature Encoder Interface enabled (x4 mode) with position counter reset by match
110 = Quadrature Encoder Interface enabled (x4 mode) with Index Pulse reset of position counter
101 = Quadrature Encoder Interface enabled (x2 mode) with position counter reset by match
100 = Quadrature Encoder Interface enabled (x2 mode) with Index Pulse reset of position counter
011 = Unused (Module disabled)
010 = Unused (Module disabled)
001 = Starts 16-bit Timer
000 = Quadrature Encoder Interface/Timer off
SWPAB: Phase A and Phase B Input Swap Select bit
1 = Phase A and Phase B inputs swapped
0 = Phase A and Phase B inputs not swapped
PCDOUT: Position Counter Direction State Output Enable bit
1 = Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin)
0 = Position Counter Direction Status Output Disabled (Normal I/O pin operation)
TQGATE: Timer Gated Time Accumulation Enable bit
1 = Timer gated time accumulation enabled
0 = Timer gated time accumulation disabled
PCDOUT
Note:
R/W-0
(Read-only bit when QEIM<2:0> = ‘1XX’)
(Read/Write bit when QEIM<2:0> = ‘001’)
U-0
—
QEIxCON: QEI CONTROL REGISTER
(MAXCNT)
(MAXCNT)
CNTERR flag only applies when QEIM<2:0> = ‘110’ or ‘100’.
W = Writable bit
‘1’ = Bit is set
QEISIDL
TQGATE
R/W-0
R/W-0
INDEX
R/W-0
R-0
Preliminary
TQCKPS<1:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
UPDN
R/W-0
POSRES
R/W-0
R/W-0
© 2008 Microchip Technology Inc.
x = Bit is unknown
QEIM<2:0>
R/W-0
R/W-0
TQCS
UPDN_SRC
R/W-0
R/W-0
bit 8
bit 0
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