AT89S8253-24AU Atmel, AT89S8253-24AU Datasheet - Page 26

• Manufacturer Part Number: AT89S8253-24AU
• Description: IC MCU 12K FLASH 24MHZ 44-TQFP
• Manufacturer: Atmel
• Series: 89Sr

Specifications of AT89S8253-24AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 14-2.
Table 14-3.
26
SPSR Address = AAH
Not Bit Addressable
Symbol
SPIF
WCOL
LDEN
DISSO
ENH
SPDR Address = 86H
Not Bit Addressable
Bit
Bit
AT89S8253
SPIF
SPD7
Function
SPI interrupt flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and ES
= 1. The SPIF bit is cleared by reading the SPI status register followed by reading/writing the SPI data register.
When ENH = 0: Write collision flag. The WCOL bit is set if the SPI data register is written during a data transfer. During
data transfer, the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and
the SPIF bit) are cleared by reading the SPI status register followed by reading/writing the SPI data register.
When ENH = 1: WCOL works in Enhanced mode as Tx Buffer Full. Writing during WCOL = 1 in enhanced mode will
overwrite the waiting data already present in the Tx Buffer. In this mode, WCOL is no longer reset by the SPIF reset but
is reset when the write buffer has been unloaded into the serial shift register.
Load enable for the Tx buffer in enhanced SPI mode.
When ENH is set, it is safe to load the Tx Buffer while LDEN = 1 and WCOL = 0. LDEN is high during bits 0 - 3 and is low
during bits 4 - 7 of the SPI serial byte transmission time frame.
Disable slave output bit.
When set, this bit causes the MISO pin to be tri-stated so more than one slave device can share the same interface with
a single master. Normally, the first byte in a transmission could be the slave address and only the selected slave should
clear its DISSO bit.
Enhanced SPI mode select bit. When ENH = 0, SPI is in normal mode, i.e. without write double buffering.
When ENH = 1, SPI is in enhanced mode with write double buffering. The Tx buffer shares the same address with the
SPDR register.
7
7
SPSR – SPI Status Register
SPDR – SPI Data Register
WCOL
SPD6
6
6
LDEN
SPD5
5
5
SPD4
–
4
4
SPD3
–
3
3
Reset Value = 00H (after cold reset)
unchanged (after warm reset)
SPD2
–
2
2
Reset Value = 000X XX00B
DISSO
SPD1
1
1
SPD0
ENH
0
0
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